tda9983bhw/8/c1 NXP Semiconductors, tda9983bhw/8/c1 Datasheet - Page 35

• Manufacturer Part Number: tda9983bhw/8/c1
• Description: Hdmi Transmitter Up To 150 Mhz Pixel Rate With 3 ? 8-bit Video Inputs And 4 ? I 2s-bus With S/pdif
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 32.
Legend: * = default value
[1]
Table 33.
Legend: * = default value
TDA9983B_1
Product data sheet
Address Register
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
Address Register
99h
9Ah
9Bh
9Ch
The value is a signed 11-bit two’s complement integer.
MAT_OO1_MSB
MAT_OO1_LSB
MAT_OO2_MSB
MAT_OO2_LSB
MAT_P11_MSB
MAT_P11_LSB
MAT_P12_MSB
MAT_P12_LSB
MAT_P13_MSB
MAT_P13_LSB
MAT_P21_MSB
MAT_P21_LSB
MAT_P22_MSB
MAT_P22_LSB
MAT_P23_MSB
MAT_P23_LSB
MAT_P31_MSB
MAT_P31_LSB
MAT_P32_MSB
MAT_P32_LSB
MAT_P33_MSB
MAT_P33_LSB
Coefficient registers (address 87h to 98h) bit description
Offset output registers (address 99h to 9Eh) bit description
Bit
7 to 3 x
2 to 0 P11[10:8]
7 to 0 P11[7:0]
7 to 3 x
2 to 0 P12[10:8]
7 to 0 P12[7:0]
7 to 3 x
2 to 0 P13[10:8]
7 to 0 P13[7:0]
7 to 3 x
2 to 0 P21[10:8]
7 to 0 P21[7:0]
7 to 3 x
2 to 0 P22[10:8]
7 to 0 P22[7:0]
7 to 3 x
2 to 0 P23[10:8]
7 to 0 P23[7:0]
7 to 3 x
2 to 0 P31[10:8]
7 to 0 P31[7:0]
7 to 3 x
2 to 0 P32[10:8]
7 to 0 P32[7:0]
7 to 3 x
2 to 0 P33[10:8]
7 to 0 P33[7:0]
Bit
7 to 3 x
2 to 0 OFFSET_OUT1[10:8] W
7 to 0 OFFSET_OUT1[7:0]
7 to 3 x
2 to 0 OFFSET_OUT2[10:8] W
7 to 0 OFFSET_OUT2[7:0]
Symbol
Symbol
Rev. 01 — 20 May 2008
Access Value
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Access Value
W
W
W
W
0000 0* undefined
010*
00h*
0000 0* undefined
110*
92h*
0000 0* undefined
111*
50h*
0000 0* undefined
010*
00h*
0000 0* undefined
010*
CEh*
0000 0* undefined
000*
00h*
0000 0* undefined
010*
00h*
0000 0* undefined
000*
00h*
0000 0* undefined
011*
8Ch*
0000 0* undefined
000*
00h*
0000 0* undefined
000*
00h*
150 MHz pixel rate HDMI transmitter
Description
coefficient (1, 1): coefficient from the
G/Y channel to the G/Y channel
coefficient (1, 2): coefficient from the
R/C
coefficient (1, 3): coefficient from the
B/C
coefficient (2, 1): coefficient from the
G/Y channel to the R/C
coefficient (2, 2): coefficient from the
R/C
coefficient (2, 3): coefficient from the
B/C
coefficient (3, 1): coefficient from the
G/Y channel to the B/C
coefficient (3, 2): coefficient from the
R/C
coefficient (3, 3): coefficient from the
B/C
Description
offset output 1: new clamp level for the
G/Y channel
offset output 2: new clamp level for the
R/C
B
B
B
R
R
R
R
channel to the G/Y channel
channel to the R/C
channel to the B/C
channel to the G/Y channel
channel to the R/C
channel to the B/C
channel
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TDA9983B
© NXP B.V. 2008. All rights reserved.
B
R
B
R
B
R
channel
channel
channel
channel
channel
channel
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