tda9983bhw/8/c1 NXP Semiconductors, tda9983bhw/8/c1 Datasheet - Page 54

• Manufacturer Part Number: tda9983bhw/8/c1
• Description: Hdmi Transmitter Up To 150 Mhz Pixel Rate With 3 ? 8-bit Video Inputs And 4 ? I 2s-bus With S/pdif
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 62.
Legend: * = default value
Table 63.
Legend: * = default value
TDA9983B_1
Product data sheet
Address Register
C3h
C4h
Address Register
C5h
C6h
C7h
C8h
VWIN_END_2_MSB
VWIN_END_2_LSB
DE_START_MSB
DE_START_LSB
DE_STOP_MSB
DE_STOP_LSB
VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description
DE_START_x and DE_STOP_x registers (address C5h to C8h) bit description
Table 64.
Legend: * = default value
Bit
7
6
5
4
3
2
Symbol
SYNC_ONCE
SYNC_MTHD
FRAME_DIS
x
TOP_EXT
DE_EXT
Bit
7 to 2 x
1 to 0 VWIN_END_2[9:8]
7 to 0 VWIN_END_2[7:0]
Bit
7 to 2 x
1 to 0 DE_START[9:8]
7 to 0 DE_START[7:0]
7 to 2 x
1 to 0 DE_END[9:8]
7 to 0 DE_END[7:0]
TBG_CNTRL_0 register (address CAh) bit description
Symbol
Symbol
Rev. 01 — 20 May 2008
Access Value
W
W
W
W
W
W
0*
1
0*
1
0*
1
0*
0*
1
0*
1
Access Value
W
W
W
Access Value
W
W
W
W
W
W
Description
sync once
sync method
frame disable: synchronized by linecnt = 1
AND pixelcnt = 1
undefined
top external
data enable external
0000 00* undefined
00*
00h*
0000 00* undefined
00*
00h*
0000 00* undefined
00*
00h*
line/pixel counters are synchronized each
frame
line/pixel counters are synchronized only
once
synchronization is based on combination of
v and h
synchronization is based on combination of
v and x (de)
enable video frames
disable video frames
top = top_tbg_sci
top = x_vip (external; fref)
de = de_tbg_sci (internal)
de = x_vip (external; de)
150 MHz pixel rate HDMI transmitter
Description
vertical window end 2: vertical
window line number for end pulse
in field 2
Description
data enable start: data enable
pixel number for start pulse in
field 1
data enable end: data enable
pixel number for end pulse in
field 2
TDA9983B
© NXP B.V. 2008. All rights reserved.
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