tda9983bhw/8/c1 NXP Semiconductors, tda9983bhw/8/c1 Datasheet - Page 42

• Manufacturer Part Number: tda9983bhw/8/c1
• Description: Hdmi Transmitter Up To 150 Mhz Pixel Rate With 3 ? 8-bit Video Inputs And 4 ? I 2s-bus With S/pdif
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 47.
Legend: * = default value
Table 48.
Legend: * = default value
Table 49.
Legend: * = default value
TDA9983B_1
Product data sheet
Address Register
E8h
E9h
EAh
Address Register
EEh
EFh
Address Register
F0h
F1h
TIMER_H
TIMER_M
TIMER_L
NDIV_IM
NDIV_PF
RPT_CNTRL
LEAD_OFF
Timer control registers (address E8h to EAh) bit description
NDIV_xxx registers (address EEh and EFh) bit description
Control registers (address F0h to F2h, F9h, FDh and FEh) bit description
9.3.7 Timer control registers
9.3.8 NDIV register
9.3.9 Control registers
Bit
7
6
5 to 2
1 to 0
7 to 0
7 to 0
Bit
7 to 4
3 to 0
7 to 0
Bit
7 to 4
3 to 0
7 to 4
3 to 0
Symbol
x
NDIV_IM[3:0]
NDIV_PF[7:0]
Symbol
x
REPEAT[3:0]
x
LEAD_OFFSET[3:0]
Symbol
IM_CLKSEL
WD_CLKSEL
x
TIM_H[1:0]
TIM_M[7:0]
TIM_L[7:0]
Rev. 01 — 20 May 2008
Access Value
W
W
W
W
Access Value
W
W
W
W
W
W
Access Value
W
W
W
0000*
0000*
0000*
0010*
0
1
0
1
0000*
00
01*
10
00
C2h*
40h*
0000*
0011*
1Bh*
150 MHz pixel rate HDMI transmitter
Description
im timer clock select
watchdog timer clock select
undefined
timer control register height
timer control register medium
timer control register low
Description
undefined
N divisor DDC-bus master
N divisor pixel frequency
Description
undefined
repeat: repeater control
undefined
leading offset: leading offset for dwin
(in case rpt > 1)
ddc_master clocked by
hdmi_clk / (NDIV_IM[3:0] + 1)
ddc_master clocked by
cclk / 3 (typically 10 MHz)
wd_timer clocked by
hdmi_clk / (NDIV_PF[7:0] + 1)
wd_timer clocked by cclk / 32
tim[17:16] = ’00’
tim[17:16] = ’01’
tim[17:16] = ’10’
tim[17:16] = ’11’
tim[15:8] = TIM_M[7:0]
tim[7:0] = TIM_L[7:0]
N divisor to set clock period for
DDC-bus master
N divisor to set clock period for timers
(equals pixel frequency)
TDA9983B
© NXP B.V. 2008. All rights reserved.
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