adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 12

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
PIN FUNCTION DESCRIPTIONS
ADSP-21161N pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).Tie or pull unused inputs to
V
Table 2. Pin Function Descriptions
Pin
ADDR23
DATA47
MS3–0
RD
DDEXT
ADDR23–0, DATA47–0, BRST, CLKOUT (Note:
These pins have a logic-level hold circuit enabled on the
ADSP-21161N DSP with ID2–0 = 00x.)
PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)
(Note: These pins have a pull-up enabled on the ADSP-
21161N DSP with ID2–0 = 00x.)
LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note:
See Link Port Buffer Control Register Bit definitions in
the ADSP-21161N SHARC DSP Hardware Reference.)
DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,
TMS,TRST, TDI (Note: These pins have a pull-up.)
or GND, except for the following:
–
–
16
0
Type
I/O/T
I/O/T
I/O/T
I/O/T
Function
External Bus Address. The ADSP-21161N outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system the bus master outputs addresses for
read/writes of the IOP registers of other ADSP-21161Ns while all other internal memory
resources can be accessed indirectly via DMA control (that is, accessing IOP DMA parameter
registers). The ADSP-21161N inputs addresses when a host processor or multiprocessing
bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0
pins maintains the input at the level it was last driven. This latch is only enabled on the
ADSP-21161N with ID2
External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these
pins. Pull-up resistors on unused data pins are not necessary. A keeper latch on the DSP’s
DATA47
on the ADSP-21161N with ID2
Note: DATA15
the link ports are disabled and will not be used. In addition, DATA7
L0DAT7
execution of 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM
(system clock speed-external port) and SDRAM (core clock or one-half the core clock speed). The
IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1
to enable this full instruction Width/No-packing Mode of operation.
Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-
sponding banks of external memory. Memory bank sizes are fixed to 16 M words for non-
SDRAM and 64 M words for SDRAM. The MS3–0 outputs are decoded memory address
lines. In asynchronous access mode, the MS3–0 outputs transition with the other address
outputs. In synchronous access modes, the MS3–0 outputs assert with the other address
lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted.
In a multiprocessor system, the MSx signals are tracked by slave SHARCs. The internal
addresses 24 and 25 are zeros and 26 and 27 are decoded into MS3–0.
Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external
memory or from the IOP registers of other ADSP-21161Ns. External devices, including
other ADSP-21161Ns, must assert RD for reading from a word of the ADSP-21161N IOP
register memory. In a multiprocessing system, RD is driven by the bus master. RD has a
20 k internal pull-up resistor that is enabled for DSPs with ID2
–
–
0) can also be used to extend the data bus if the link ports are not used. This enables
16 pins maintains the input at the level it was last driven. This latch is only enabled
–
8 pins (multiplexed with L1DAT7
–
0=00x.
–12–
–
The following symbols appear in the Type column of
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State (when SBTS is
asserted or when the ADSP-21161N is a bus slave).
Unlike previous SHARC processors, the ADSP-21161N
contains internal series resistance equivalent to 50
input/output drivers except the CLKIN and XTAL pins.
Therefore, for traces longer than six inches, external series
resistors on control, data, clock, or frame sync pins are not
required to dampen reflections from transmission line effects for
point-to-point connections. However, for more complex
networks such as a star configuration, series termination is still
recommended.
0=00x.
–
0) can also be used to extend the data bus if
–
0 pins (multiplexed with
–
0=00x.
–
0=0x1)
on all
Table
REV. A
2: