adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 43

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 29. Serial Ports
1
Table 30. Serial Ports
1
Table 31. Serial Ports
1
2
3
Table 32. Serial Ports
1
2
3
REV. A
Parameter
Timing Requirements
t
t
t
t
t
t
Referenced to sample edge.
Parameter
Timing Requirements
t
t
t
t
Referenced to sample edge.
Parameter
Switching Characteristics
t
t
t
t
Referenced to drive edge.
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
Parameter
Switching Characteristics
t
t
t
t
t
Referenced to drive edge.
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DDTE
HDTE
DFSI
HOFSI
DDTI
HDTI
SCLKIW
Transmit/Receive FS Setup Before Transmit/Receive
SCLK
Transmit/Receive FS Hold After Transmit/Receive
SCLK
Receive Data Setup Before Receive SCLK
Receive Data Hold After Receive SCLK
SCLKx Width
SCLKx Period
FS Setup Time Before SCLK (Transmit/Receive Mode)
FS Hold After SCLK (Transmit/Receive Mode)
Receive Data Setup Before SCLK
Receive Data Hold After SCLK
FS Delay After SCLK (Internally Generated FS)
FS Hold After SCLK (Internally Generated FS)
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
FS Delay After SCLK (Internally Generated FS)
FS Hold After SCLK (Internally Generated FS)
SCLK Width
1
1
–
–
–
–
External Clock
Internal Clock
External Clock
Internal Clock
2
1
1, 2
1, 2
1
1, 2
1, 2
1
1
–43–
1
1, 2 , 3
1, 2, 3
1, 2, 3
1, 2, 3
1
Min
3.5
4
1.5
4
7
2t
Min
8
0.5t
4
3
Min
3
0
Min
–1.5
0
0.5t
CCLK
CCLK
SCLK
–2.5
+1
Max
Max
Max
13
16
Max
4.5
7.5
0.5t
ADSP-21161N
SCLK
+2
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns