adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 47

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

SPI Interface Specifications
Table 35. SPI Interface Protocol
Table 36. SPI Interface Protocol
1
2
REV. A
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
When CPHASE = 0 and baud rate is greater than 1, t
Applies to the first deassertion of SPIDS only.
SSPIDM
HSPIDM
SPITDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM_0
SDSCIM_1
HDSM
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
HDLSBS
DSOV
2
1
1
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted
CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulsewidth (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0.25t
SPICLK Edge to Last Bit Out Not Valid
(Data Out Hold Time) for LSB
SPIDS Assertion to Data Out Valid (CPHASE = 0)
Data Input Valid to SPICLK Edge (Data Input Set-up
Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge
for CPHASE = 0
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge
for CPHASE = 1
Last SPICLK Edge to FLAG3–0 High
Sequential Transfer Delay
–
–
Master Switching and Timing
Slave Switching and Timing
HDLSBS
affects the length of the last bit transmitted.
–47–
Min
8t
4t
4t
3.5t
1.5t
0
t
t
2
1.5
0.5t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SPICLK
+1
CCLK
–4
–4
Min
0.5t
0.5t
2t
8 t
4t
4t
5t
3t
t
+8
+8
CCLK
+4.5t
+3
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
–3
–4
–4
CCLK
+10
+1
ADSP-21161N
Max
3
Max
0.5t
0.5t
0.75t
1.5t
CCLK
CCLK
CCLK
CCLK
+5.5
+5.5
+7
+3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns