adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 24

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
protection circuitry. With this technique, if the 1.8 V rail rises
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail
along with the 1.8 V rail.
Clock Input
In systems that use multiprocessing or SBSRAM, CLKDBL
cannot be enabled nor can the systems use an external crystal as
the CLKIN source.
Do not use CLKOUT as the clock source for the SBSRAM
device. Using an external crystal in conjunction with CLKDBL
to generate a CLKOUT frequency is not supported. Negative
hold times can result from the potential skew between CLKIN
and CLKOUT.
Table 10. Clock Input
1
Clock Signals
The ADSP-21161N can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21161N to use its internal clock generator by connecting
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired t
CK
CKL
CKH
CKRF
CCLK
DCKOO
CKOP
CKWH
CKWL
CLKOUT
CLKOUT
NOTES:
1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN
2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN
CLKIN
APPLIES TO THE RISING EDGE, ONLY.
APPLIES TO THE RISING OR FALLING EDGE.
t
t
DCKOO
DCKOO
1
2
t
CKWH
Figure 14. Clock Input
2
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
CCLK Period
CLKOUT Delay After CLKIN
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
t
CKH
t
t
CKWH
CKOP
t
DCKOO
2
1
2
t
CKOP
t
CK
t
1
CKWL
t
1
CKL
t
2
CKWL
1
1
1
–24–
the necessary components to CLKIN and XTAL.
shows the component connections used for a crystal operating in
fundamental mode.
DC INPUT
SOURCE
Figure 15. 100 MHz Operation (Fundamental Mode
Crystal)
SUGGESTED COMPONENTS FOR 100MHz OPERATION:
ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)
C1 = 27pF
C2 = 27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz
CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK
WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.
Min
20
7.5
7.5
10
0
t
t
t
CKOP
CKOP
CKOP
Figure 13. Dual Voltage Schottky Diode
C1
27pF
/2–2
/2–2
–1
CLKIN
REGULATOR
REGULATOR
1.8V CORE
VOLTAGE
VOLTAGE
3.3V I/O
CCLK
100 MHz
.
Max
238
119
119
3
30
2
t
t
t
X1
CKOP
CKOP
CKOP
/2+2
/2+2
+1
XTAL
V
V
C2
27pF
DDEXT
DDINT
ADSP-21161N
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 15
REV. A