adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 21

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Use the exact timing information given. Do not attempt to derive
parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect sta-
tistical variations and worst cases. Consequently, it is not
meaningful to add parameters to derive longer times.
See
reference levels.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching charac-
teristics describe what the processor will do in a given circum-
stance. Use switching characteristics to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
Table 6. Operation Types Versus Input Current
1
2
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by:
The load capacitance should include the processor package
capacitance (C
load high and then back low. At a maximum rate of 1/t
address and data pins can drive high and low, while writing to a
SDRAM memory.
Example: Estimate P
REV. A
Operation
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
The number of output pins that switch during each cycle
(O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
A system with one bank of external memory (32 bit)
Two 1M
of 10 pF (ignoring trace capacitance)
Figure 40 on Page 51
IN
16 SDRAM chips are used, each with a load
). The switching frequency includes driving the
P
EXT
EXT
=
2
with the following assumptions:
O C V
under Test Conditions for voltage
DD
)
Peak Activity
(I
2 per t
1 per 2 t
1 per external port cycle ( 32)
Multifunction
Cache
Worst case
DDINPEAK
DD
CK
2
CCLK
cycle (DM 64 and PM 64)
)
f
cycles
1
CK
,
–21–
Power Dissipation
Total power dissipation has two components: one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation depends on the instruction execution
sequence and the data operands involved. Using the current spec-
ifications (I
Electrical Characteristics
operation information in
the ADSP-21161N’s internal power supply (V
current for a specific application, according to the following
formula:
The P
drive, as shown in
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Where:
P
P
Dissipation on Page
P
Characteristics
EXT
INT
PLL
External Data Memory writes can occur every cycle at a
rate of 1/t
The bus cycle time is 50 MHz
The external SDRAM clock rate is 100 MHz
Ignoring SDRAM refresh cycles
Addresses are incremental and on the same page
CK
is AI
is I
is from
and t
EXT
High Activity
(I
Multifunction
Internal Memory
1 per t
1 per 2 t
1 per external port cycle ( 32) N/A
Random
DDINT
DDINHIGH
DD
equation is calculated for each class of pins that can
CCLK
DDINPEAK
× 1.8 V, using the value for AI
Table
CK
× 1.8 V, using the calculation I
CK
), see the timing ratio definitions
P
CCLK
on Page
with 50% of the pins switching
TOTAL
cycle (DM 64)
)
% High I
% Peak I
Table
7.
, I
% Low I
+ % Idle I
--------------------------------------------------
21.
cycles
DDINHIGH
1
=
18.
Table
7.
on Page 18
I
DDINT
P
EXT
, I
DDINPEAK
DDINHIGH
DDINLOW
DDINLOW
6, the programmer can estimate
DDIDLE
+
ADSP-21161N
P
INT
and the current-versus-
, I
DD
+
DDIDLE
Low Activity
(I
Single Function
Internal Memory
None
N/A
N/A
listed in the Electrical
P
on Page
DDINT
DDINLOW
PLL
DDINT
) from the
listed in
20.
) input
)
1
Power