adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 23

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

Power-Up Sequencing – Silicon Revision 1.2
The timing requirements for DSP startup for silicon with revision
1.2 are given in
Table 9. Power-Up Sequencing for Revision 1.2 (DSP Startup)
1
2
3
4
5
RSTOUT does not currently exist for ADSP-21161N revisions
0.3, 1.0, and 1.1. This new signal will be placed on one of the
current no-connect pins: ball B15.
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
REV. A
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Requirements
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for
Based on CLKIN cycles
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly
The 4080 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
WRST
CORERST
of milliseconds depending on the design of the power supply subsystem.
start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
initialize and propagate default states at all I/O pins.
time, resulting in 4081 cycles maximum.
DDINT
/V
DDEXT
Table
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Subsequent RESET Low Pulsewidth
DSP core reset deasserted after RESET deasserted
DDINT
assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds
9.
VDDINT
VDDEXT
CLKIN
CLKDBL
RSTOUT
RESET
CLK_CFG1-0
on Before V
Figure 12. Power-Up Sequencing for Revision 1.2 (DSP Startup)
SRST
specification in
t
DDEXT
RSTVDD
DDINT
DDINT
t
IVDDEVDD
/V
/V
t
DDEXT
CLKVDD
Table
DDEXT
11. If setup time is not met, one additional CLKIN cycle may be added to the core reset
Valid
on
4
1
2
–23–
t
PLLRST
t
3
CLKRST
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
t
CORERST
Min
0
–50
0
10
20
4t
4080t
CK
CK
3, 5
ADSP-21161N
Max
+200
200
Figure
13. It protects the
Unit
ns
ms
ms
µs
µs
ns