adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 25

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adsp-21161n

Manufacturer Part Number
adsp-21161n
Description
Dsp Microcomputer
Manufacturer
Analog Devices, Inc.
Datasheet

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Reset
Table 11. Reset
1
2
Interrupts
Table 12. Interrupts
1
2
REV. A
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete.
Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
Parameter
Timing Requirements
t
t
t
Only required for IRQx recognition in the following cycle.
Applies only if t
WRST
SRST
ADSP-21161Ns communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically
after reset.
SIR
HIR
IPW
SIR
RESET Pulsewidth Low
RESET Setup Before CLKIN High
IRQ2–0 Setup Before CLKIN
IRQ2–0 Hold After CLKIN
IRQ2–0 Pulsewidth
and t
HIR
requirements are not met.
CLKIN
RESET
2
IRQ2–0
CLKIN
1
1
1
Figure 17. Interrupts
2
Figure 16. Reset
t
IPW
t
WRST
Min
4t
8.5
–25–
CK
t
SIR
Min
6
0
2 + t
t
HIR
CKOP
t
Max
SRST
Max
ADSP-21161N
Unit
ns
ns
Unit
ns
ns
ns

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