adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 22

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
Table 7. External Power Calculations (3.3 V Device)
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Table 8. Power-Up Sequencing for Revisions 0.3, 1.0, and 1.1 (DSP Startup)
1
2
3
Pin Type
Address
MSx
SDWE
Data
SDCLK0
Parameter
Timing Requirements
t
t
t
t
t
t
t
The minimum 0.9 V/ms is based on the slowest allowable ramp-up time (2 ms) for V
The minimum time of 0 ns assumes that V
The 100 µs minimum assumes a stable CLKIN signal after meeting worst-case start-up timing of crystal oscillator circuits. Refer to the crystal oscillator
RSTVDD
VDDRAMP
IVDDEVDD
CLKVDD
VDDRST
CLKRST
PLLRST
ramp from 0 volts to 3.3 volts.
1.8 and 3.3 volt rails before RESET can be deasserted.
manufacturer's data sheet for start-up time. A 25 ms maximum oscillator start-up time can be assumed if using the XTAL pin and internal oscillator
circuit in conjunction with an external crystal. 100 µs is the minimum time required for the PLL to reliably lock to a valid (stable) CLKIN frequency.
Number of Pins
11
4
1
32
1
VDDINT
VDDEXT
CLKIN
CLKDBL
RESET
CLK_CFG1-0
Figure 11. Power-Up Sequencing for Revisions 0.3, 1.0, and 1.1 (DSP Startup)
RESET Low Before V
V
V
CLKIN Valid After V
V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
DDINT
DDINT
DDINT
/V
/V
on Before V
DDEXT
DDEXT
INT
t
t
VDDRAMP
. Maximum P
RSTVDD
DDINT
t
Voltage Ramp Rate
Valid Before RESET Deasserted
VDDRAMP
t
IVDDEVDD
and V
% Switching
20
0
0
50
100
DDEXT
t
CLKVDD
DDINT
EXT
DDINT
DDEXT
INT
are different
/V
/V
cannot
power supplies are valid. The V
DDEXT
DDEXT
1
Valid
on
–22–
24.7 pF
24.7 pF
24.7 pF
14.7 pF
24.7 pF
C
3
Power-Up Sequencing – Silicon Revision 0.3, 1.0, 1.1
The timing requirements for DSP startup for silicon revision 0.3,
1.0, or 1.1 are given in
t
VDDRST
DDINT
2
t
CLKRST
to ramp from 0 volts to 1.8 volts and (3.6 ms) for V
DDINT
50 MHz
N/A
N/A
50 MHz
100 MHz
t
PLLRST
f
and V
Table
DDEXT
8.
Min
0
0.0009
–50
0
100
100
20
supplies must be fully ramped to their
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
V
DD
2
Max
9
+200
200
P
= P
= 0.030 W
= 0.000 W
= 0.000 W
= 0.128 W
= 0.027 W
EXT
EXT
= 0.185 W
Unit
ns
V/µs
ms
ms
µs
µs
µs
DDEXT
REV. A
to