adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet - Page 50

• Manufacturer Part Number: adsp-21161n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-21161N
JTAG Test Access Port and Emulation
Table 37. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR,
System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
SBTS, ID2–0, IRQ2–0, RESET, BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS,
SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.
CAS, SDCLK1–0, SDCKE, BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10,
TIMEXP, EMU, BMSTR, RSTOUT.
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth
TDO Delay from TCK Low
System Outputs Delay After TCK Low
TCK
TMS
TDO
SYSTEM
OUTPUTS
TDI
INPUTS
SYSTEM
Figure 36. JTAG Test Access Port and Emulation
t
DTDO
t
TCK
t
DSYS
t
STAP
1
1
2
–50–
t
HTAP
Min
t
5
6
2
15
4t
CK
CK
t
SSYS
Max
13
30
t
HSYS
Unit
ns
ns
ns
ns
ns
ns
ns
ns
REV. A