ade7854 Analog Devices, Inc., ade7854 Datasheet
ade7854
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ade7854 Summary of contents
Page 1
... The ADE7854 is suitable to measure active and apparent energy in various 3-phase configurations, such as WYE or DELTA services, with both three and four wires. The ADE7854 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, ...
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... ADE7854 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings .......................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Terminology .................................................................................... 13 Typical Performance Characteristics ........................................... 14 Test Circuits ..................................................................................... 15 Power Management ........................................................................ 16 PSM0 – Normal Power Mode ............................................... 16 PSM3 – Sleep Mode ............................................................... 16 Power Up Procedure .............................................................. 16 Hardware Reset ...
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... Preliminary Technical Data HSDC Interface ....................................................................... 50 Registers List .................................................................................... 54 Outline Dimensions ........................................................................ 69 Ordering Guide ........................................................................... 69 Rev. PrC| Page ADE7854 ...
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... HPF AVRMSOS AWATTOS LPF Σ AVGAIN HPFDIS[23:0] HPF AVAROS Computational Σ Block for Total Reactive Power Digital Integrator Figure 1. ADE7854 Functional Block Diagram Rev. PrC| Page Preliminary Technical Data AVAGAIN AIRMS AVRMS CFxDEN AWGAIN DFC : CFxDEN Phase : A,B and DFC C data ...
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... Nominal 1 REF ±0.9 mV max 4 kΩ min 10 ppm/°C typ 50 ppm/°C max All specifications CLKIN of 16.384 MHz 16.384 MHz max 30 KΩ min Rev. PrC| Page ADE7854 −40°C to +85°C. MIN MAX pin IN/OUT ...
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... POWER SUPPLY in PSM3 modes VDD I in PSM3 mode DD 1 See the Typical Performance Characteristics. 2 See the Terminology section for a definition of the parameters. 3 See Power Management chapter for details on various power modes of the ADE7854 Specification Unit Test Conditions/Comments 50 KΩ max 12 pF typ 12 pF typ 2 ...
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... MIN MAX Standard mode Fast Mode Min Max Min 0 100 0 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 3.45 0 250 100 1000 20 300 20 4.0 0.6 4.7 1 HD;STA SU;STO STOP CONDITION ADE7854 Max Unit 400 kHz μs μs μs μs 0.9 μs ns 300 ns 300 ns μs μ BUF START CONDITION ...
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... ADE7854 Table 3. SPI INTERFACE TIMING Parameter Parameter SS to SCLK edge SCLK period SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time ...
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... Figure 4. HSDC Interface Timing 200µ OUTPUT PIN C L 50pF 1.6mA I OH Figure 5. Load Circuit for Timing Specifications Rev. PrC| Page Min Max 0 125 SFS DIS LSB t DR 2.1V ADE7854 Unit ...
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... ADE7854 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Absolute Maximum Ratings Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND ...
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... Power Mode pin 0. This pin should be set to VDD via a 10kΩ pull-up resistor for proper operation of the ADE7854. Power Mode pin 1. This pin defines the power mode of the ADE7854 as described in Table 7. Reset Input, active low. This pin provides access to the on-chip 2.5V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 4.7 μ ...
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... A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7854. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a detailed presentation of the events that may trigger interrupts ...
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... Gain Error The gain error in the ADCs of the ADE7854 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). The difference is expressed as a percentage of the ideal code ...
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... ADE7854 TYPICAL PERFORMANCE CHARACTERISTICS TBD Preliminary Technical Data Rev. PrC| Page ...
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... Preliminary Technical Data TEST CIRCUITS TBD Figure 7. Test Circuit for Integrator Off TBD Figure 8. Test Circuit for Integrator On Rev. PrC| Page ADE7854 ...
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... PSM0 – normal power mode PSM3 – sleep mode PSM0 – Normal Power Mode In this mode, the ADE7854 is fully functional. The PM1 pin is set to low for the ADE7854 to enter this mode. If the ADE7854 is in PSM3 mode and is switched into PSM0 mode, then all control registers take the default values. The ...
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... Bit 7 (SWRST) in CONFIG[15:0] register manages the software reset functionality in PSM0 mode. The default value of this bit this bit is set to 1, then the ADE7854 enters a software reset state. In this state, almost all internal registers are set to their default value. In addition, the choice of what serial port ...
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... ADE7854 Power Mode Registers State after Set to software reset default PSM3 Not available Table 9. Recommended actions when changing power modes Initial Power Recommended actions before setting next power Mode mode PSM0 -stop DSP by setting RUN[15:0]=0x0000 -disable HSDC by clearing bit 6 (HSDEN ...
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... ANALOG LOW-PASS FILTER R A Σ - ∆ modulator converts the input signal into a continuous serial stream of 1s and rate determined by the sampling IAP, IBP or clock. In the ADE7854, the sampling clock is equal to V ICP 1 + 1.024MHz (CLKIN/16). The 1-bit DAC in the feedback loop is driven by the serial data stream ...
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... ADE7854 ADE7854 is 1.024MHz and the band of interest kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered — see Figure 14 ...
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... In addition, waveform samples are also scaled accordingly. Note that the serial ports of the ADE7854 work on 32 bit words and the DSP works on 28 bits. The 24-bit AIGAIN, BIGAIN and CIGAIN registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits ...
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... DICOEFF[23:0] is not used when the integrator is turned off and can be left at 0x000000 in this case. As previously stated, the serial ports of the ADE7854 work on 32 8-bit words. Similar to the registers presented in Figure 16, DICOEFF[23:0] 24-bit signed register is accessed as a Rev. PrC| Page ...
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... Preliminary Technical Data 32-bit register with 4 most significant bits padded with 0s and sign extended to 28 bits. When the digital integrator is switched off, the ADE7854 can be used directly with a conventional current sensor, such as a current transformer (CT). VOLTAGE CHANNEL ADC Figure 25 shows the ADC and signal processing chain for the input VA in the voltage channel ...
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... B data path, phase B voltage is used in phase C data path and phase C voltage is used in phase A data path. POWER QUALITY MEASUREMENTS Zero Crossing Detection The ADE7854 has a zero-crossing (ZX) detection circuit on the current and voltage channels. Zero crossing events are used as a Rev. PrC| Page Preliminary Technical Data ...
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... STATUS1 register with the status bit SEQERR set to 1. The phase sequence error detection circuit is functional only when the ADE7854 is connected phase 4 wire 3 voltage sensors configuration (bits 5,4 CONSEL in ACCMODE[7:0] set to 00). In all other configurations, only two voltage sensors are Rev ...
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... Figure 30. Phase Sequence Detection Time Interval Between Phases The ADE7854 has the capability to measure the time delay between phase voltages, between phase currents or between voltages and currents of the same phase. The negative to positive transitions identified by the zero crossing detection circuit are used as start and stop measuring points ...
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... and f is 50Hz or 60Hz. Line Period Measurement The ADE7854 provides the period measurement of the line in the voltage channel. Bits 1,0 (PERSEL[1:0]) in MMODE[7:0] register select the phase voltage used for this measurement. The PERIOD register is a 16-bit unsigned register and is updated every line period ...
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... Voltage Channel ADC Chapter, so the sag event is triggered continuously. Writing 0x00 or 0x01 puts the sag detection level the sag event is never triggered. As previously stated, the serial ports of the ADE7854 work on 32 8-bit words. Similar to the register presented in Figure 17, SAGLVL register is accessed as 32-bit registers with 8 most significant bits padded with 0s ...
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... PEAKCYC period. Overvoltage and Overcurrent Detection The ADE7854 detects when the instantaneous absolute value measured on the voltage and current channels becomes greater than thresholds set in OVLVL[23:0] and OILVL[23:0] 24-bit unsigned registers. If bit 18 (OV) in MASK1[31:0] register is ...
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... The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7854 provides a means of digitally calibrating these small phase errors. The ADE7854 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors. ...
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... IN/OUT source, for example, an external 1.2 V reference. The voltage of the ADE7854 reference drifts slightly with temperature; see the Specifications section for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Because the reference is used for all ADCs, any x% drift in the reference results in a 2x% deviation of the meter accuracy ...
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... RAM with their desired values and then write RUN[15:0] register with 0x0001. In this way, the DSP starts the computations from a desired configuration. There is no obvious reason to stop the DSP if the ADE7854 is maintained in PSM0 normal mode. All ADE7854 registers including ones located in the data memory RAM can be modified without stopping the DSP ...
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... Table 11. Settling Time for VRMS Measurement 50Hz Input signals 530 ms As previously stated, the serial ports of the ADE7854 work on 32 8-bit words. Similar to the register presented in Figure 17, AVRMS, BVRMS and CVRMS 24-bit signed registers are accessed as 32-bit registers with 8 most significant bits padded with 0s ...
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... ADE7854 As previously stated, the serial ports of the ADE7854 work on 32 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 16, AVRMSOS, BVRMSOS and CVRMSOS 24-bit registers are accessed as 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits ...
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... These registers can be used to calibrate the active power (or energy) calculation in the ADE7854 for each phase. As previously stated, the serial ports of the ADE7854 work on 32 8-bit words and the DSP works on 28 bits. Similar to registers presented in Figure 16, AWGAIN, BWGAIN, ...
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... The minimum value is 0x0, but it is recommended to write a number equal or greater than PMAX. Negative numbers should never be used. The WTHR[47: 48-bit register. As previously stated, the serial ports of the ADE7854 work on 32 8-bit words. As presented in Figure 47, WTHR register is accessed as two 32-bit total active powers. Digital ...
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... In line cycle energy accumulation mode, the ADE7854 transfers the active energy accumulated in the 32-bit internal accumulation registers into xWATHHR[31:0], x=A,B,C registers after an integral number of line cycles, as shown in Figure 48 ...
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... The ADE7854 computes the arithmetic apparent power on each phase. Figure 49 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7854. As VRMS and IRMS contain all harmonic information, the apparent power computed by the ADE7854 is a total apparent power ...
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... FS FS the ADC inputs are at full scale. The VATHR[47: 48-bit register. As previously stated, the serial ports of the ADE7854 work on 32 8-bit words. Similar to the WTHR[47:0] register presented in Figure 47, VATHR[47:0] is accessed as two 32-bit registers (VATHR1[31:0] and VATHR0[31:0]), each having 8 most significant bits padded with 0s ...
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... In this mode, the ADE7854 transfers the apparent energy accumulated in the 32-bit internal accumulation registers into xVAHR[31:0], x=A,B,C registers after an integral number of line cycles, as shown in Figure 50 ...
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... Two sets of bits decide what powers are converted. First, bits (TERMSEL1[2:0]), (TERMSEL2[2:0]) and (TERMSEL3[2:0]) of COMPMODE[15:0] register As previously stated, the serial ports of the ADE7854 work on Description 32 8-bit words. All registers listed in Table 15 are power transmitted signed extended from bits (see Figure 18) ...
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... If CFxDEN is set equal to 0, then the ADE7854 considers it as equal to 1. The pulse output for all digital to frequency converters stays low for 80ms if the pulse period is larger than 160ms (6.25Hz). If the pulse period is smaller than 160ms, the duty cycle of the pulse output is 50% ...
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... CF pulses are generated based on the absolute accumulation mode. Sign of sum of phase powers in CFx data path The ADE7854 has a sign detection circuitry for the sum of phase powers that are used in CFx, x= data path. As seen in the beginning of ENERGY to FREQUENCY CONVERSION chapter, the energy accumulation in CFx data path is executed in two stages ...
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... When VANOLOAD[23:0] is set to negative values, the no load detection circuit is disabled. As previously stated, the serial ports of the ADE7854 work on 32 8-bit words and the DSP works on 28 bits. Similar to registers presented inFigure 16, VANOLOAD 24-bit signed register is accessed as a 32-bit registers with 4 most significant bits padded with 0s and sign extended to 28 bits ...
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... ADE7854 has changed configuration. The recommended response is to initiate a hardware/software reset that sets the values of all registers to the default, including the reserved ones, and then reinitialize the configuration registers ...
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... Then, the same STATUSx content is written back into the ADE7854 to clear the status flag(s) and reset IRQx line to logic high ( that event is recorded by the MCU external interrupt flag 3 being set again ...
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... JUMP INTERRUPT INTERRUPT SEQUENCE to ISR MASK Figure 59. ADE7854 interrupt management when PHSTATUS, IPEAK, VPEAK or PHSIGN registers are involved SERIAL INTERFACES The ADE7854 has three serial port interfaces: one fully licensed interface, one Serial Peripheral Interface (SPI) and one High Speed Data Capture Port (HSDC). As the SPI pins are ...
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... Data is shifted into the ADE7854 at the MOSI logic input on the falling edge of SCLK. Data is shifted out of the ADE7854 at the MISO logic output on a rising edge of SCLK. The most significant bit of the word is shifted in and out first. The maximum serial clock frequency supported by this interface is 2 ...
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... WRITE ) of the address byte must be 1 for a read operation. Next, the master sends the 16-bit address of the SCK register that is read. After the ADE7854 receives the last bit of address of the register on a low to high transition of SCLK, it begins to transmit its content on the MISO line before the next ...
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... Figure 64. SPI Write operation of a 32-bit register See Figure 64 for details of the SPI write operation. HSDC Interface The High Speed Data Capture (HSDC) interface is disabled after default. It can be used only if the ADE7854 are configured 2 with I conjunction with HSDC. Bit 6 (HSDCEN) in CONFIG[15:0] register activates HSDC when set to 1 ...
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... HSCLK is the serial clock line generated by the ADE7854 and is usually connected to the serial clock input of the slave. Figure 65 and Figure 66 present details of connections between ADE7854 HSDC and slave devices containing SPI and SPORT interfaces ...
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... ADE7854 for HXFER[1:0] is reserved and writing it is equivalent to writing 00, the default value. Bit 5 (HSAPOL) determines the polarity of HSA pin during the communication. When HSAPOL is 0, the default value, the HSA pin is active low during the communication. This means that HSA stays high when no communication is in progress. ...
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... HSDATA IAVW (Byte 3) HSACTIVE Figure 69. HSDC communication for HSIZE=1, HGAP=1, HXFER[1:0]=00 and HSAPOL IBWV(32bit) 7 HCLK 7 HCLK cycles cycles 23 16 IAWV (Byte 2) 7 HCLK 7 HCLK cycles cycles Rev. PrC| Page ADE7854 ICWV(32bit) CVA (32bit IAWV(Byte 1) CVA(Byte ...
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... ADE7854 REGISTERS LIST Table 19. ADE7854 Registers List located in DSP data memory RAM Bit 1 Address Name R/W Length 0x4380 AIGAIN R/W 24 0x4381 AVGAIN R/W 24 0x4382 BIGAIN R/W 24 0x4383 BVGAIN R/W 24 0x4384 CIGAIN R/W 24 0x4385 CVGAIN R/W 24 0x4386 Reserved 0x4387 AIRMSOS R/W 24 0x4388 AVRMSOS R/W 24 0x4389 BIRMSOS R/W 24 0x438A BVRMSOS R/W 24 0x438B CIRMSOS R/W 24 0x438C ...
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... Phase A voltage rms value Phase B current rms value Phase B voltage rms value Phase C current rms value Phase C voltage rms value 0x000000 These memory locations should not be written for proper operation Rev. PrC| Page ADE7854 ...
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... ADE7854 Table 20. Internal DSP memory RAM registers Bit 1 Address Name R/W Length 0xE203 reserved R/W 16 0xE228 RUN R R=read W=write 2 U=unsigned register S=signed register in two’s complement format Bit Length during Default 2 Comm Type Value 16 U 0x0000 16 U 0x0000 Rev. PrC| Page ...
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... Preliminary Technical Data Table 21. ADE7854 billable registers Bit Address Name R/W 1 Length 0xE400 AWATTHR R 32 0xE401 BWATTHR R 32 0xE402 CWATTHR R 32 0xE403- Reserved R 0xE40B 0xE40C AVAHR R 32 0xE40D BVAHR R 32 0xE40E CVAHR R=read W=write 2 U=unsigned register S=signed register in two’s complement format ...
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... ADE7854 Table 22. Configuration and power quality registers Bit 1 Address Name R/W Length 0xE500 IPEAK R 32 0xE501 VPEAK R 32 0xE502 STATUS0 R 32 0xE503 STATUS1 R 32 0xE504- Reserved R 0xE506 0xE507 OILVL R/W 24 0xE508 OVLVL R/W 24 0xE509 SAGLVL R/W 24 0xE50A MASK0 R/W 32 0xE50B MASK1 R/W 32 0xE50C IAWV R 24 0xE50D IBWV ...
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... CF3 denominator Phase calibration of phase A. (Table 35 ). Phase calibration of phase B. (Table 35 ) Phase calibration of phase C. (Table 35) Power sign register. (Table 36) ADE7854 configuration register. (Table 37) Measurement mode register. (Table 38) Accumulation mode register. (Table 39) Line accumulation mode behavior. (Table 40). Peak detection half line cycles Sag detection half line cycles Number of CF pulses between two consecutive energy latches ...
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... ADE7854 Table 23. HPFDIS register (address 0x43B6) Bit Bit Default Location Mnemonic value 23:0 00000000 Table 24. IPEAK register (address 0xE500) Bit Location Bit Mnemonic Default value 23-0 IPEAKVAL[23: IPPHASE[ IPPHASE[ IPPHASE[2] 0 31-27 00000 Table 25. VPEAK register (address 0xE501) Bit Location Bit Mnemonic ...
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... When this bit is set indicates that the sum of all phase powers in the CF3 data path has changed sign. The sign itself is indicated in bit 8 (SUM3SIGN) of PHSIGN[15:0] register (see Table 36). These bits are always 0. Rev. PrC| Page ADE7854 IRQ 1 pin goes low to signal this moment ...
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... ADE7854 Table 28. MASK0 register (address 0xE50A) Bit Bit Default Location Mnemonic value 0 AEHF 0 1-3 Reserved 000 4 VAEHF 0 5 LENERGY 0 6 REVAPA 0 7 REVAPB 0 8 REVAPC 0 9 REVPSUM1 0 10-12 Reserved 000 13 REVPSUM2 0 14 CF1 15 CF2 16 CF3 17 DREADY 0 18 REVPSUM3 0 31-18 Reserved 00 0000 0000 0000 Table 29. MASK1 register (address 0xE50B) ...
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... load condition based on apparent power. Bit set together with bit 2 (VANLOAD) in STATUS1[31:0]. -0: phase C is out of no-load condition based on apparent power. -1: phase load condition based on apparent power. Bit set together with bit 2 Rev. PrC| Page ADE7854 ...
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... C is computed using VNOM[23:0] register instead of regular measured rms phase voltage. When the ADE7854 is connected to 50Hz networks, this bit should be cleared to 0 (default value). When the ADE7854 is connected to 60Hz networks, this bit should be set to 1. This bit does not manage any functionality. ...
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... COMPMODE[15:0] register. -011,100: if selected, CF3 pin is set low permanently. -101,110,111: reserved. When set, the ADE7854 behaves like CF3SEL [2:0]=000. When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency converter remains enabled even if CF1DIS=1. When set to 0, the CF1 output is enabled. ...
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... These bits decide what phase voltage is considered together with phase C current in the power path: 00=phase C voltage 01=phase A voltage 10=phase B voltage 11=reserved. When set, the ADE7854 behaves like VTOIC [1:0]=00 These bits do not manage any functionality. Rev. PrC| Page Preliminary Technical Data ...
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... Description -00: signed accumulation mode of the total active powers -01: reserved. When set, the ADE7854 behaves like WATTACC[1:0]=00 -10: reserved. When set, the ADE7854 behaves like WATTACC[1:0]=00 -11: absolute accumulation mode of the total active powers These bits do not manage any functionality These bits are used to select the inputs to the energy accumulation registers: ...
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... CONFIG2[7:0] register locks the port. From this moment on, a switch into using I port is no longer possible. Once locked, the serial port choice is maintained when the ADE7854 changes between PSM0 and PSM3 power modes. These bits do not manage any functionality. ...
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... OUTLINE DIMENSIONS ORDERING GUIDE Model Temperature Range ADE7854ACPZ −40°C to +85°C ADE7854ACPZ-RL −40°C to +85°C EVAL-ADE7854EBZ Figure 70. 40LFCSP ( mm), CP-40-1 Dimensions shown in millimeters Package Description 40-Lead LFCSP 40-Lead LFCSP, Reel ADE7854 evaluation board Rev. PrC | Page ADE7854 Package Option CP-40-1 CP-40-1 ...
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... ADE7854 NOTES Preliminary Technical Data Rev. PrC | Page ...
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... Preliminary Technical Data NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR08017-0-2/09(PrC) Rev. PrC | Page ADE7854 ...