ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 42

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
By default, TERMSELx bits are all 1 and CF1SEL bits are 000,
CF2SEL bits are 001 and CF3SEL bits are 010. This means that
by default, the CF1 digital to frequency converter produces
signals proportional to the sum of all 3 phase total active
Table 16. CFxSEL, x=1,2,3 bits description
CFxSEL
000
001
010
011-111
Similar to the energy accumulation process, the energy to
frequency conversion is done in two stages. In the first stage,
the instantaneous phase powers obtained from the DSP at 8KHz
rate are shifted left 7 bits and then accumulated into a 55 bit
register at 1MHz rate. When a threshold is reached, a pulse is
generated and the threshold is subtracted from the internal
register. The sign of the energy in this moment is considered the
sign of the sum of phase powers (see Sign of sum of phase
powers in CFx data path section for details). The threshold is
the same threshold used in various active and appearent energy
accumulators in DSP, WTHR[47:0] or VATHR[47:0], but this
time it is shifted left 7 bits. The advantage of accumulating the
instantaneous powers at 1MHz rate is that the ripple at CFx pins
is greatly diminished. The second stage consists in a frequency
divider by CFxDEN[15:0], x=1,2,3, 16-bit unsigned registers.
The values of CFxDEN depend on the meter constant (MC),
measured in impulses/kwh and how much energy is assigned to
1LSB of various energy registers: WATT-hr and VA-hr. Let’s
suppose a derivative of wh, [10
integer, is desired as 1LSB of WATTHR. Then CFxDEN is:
The derivative of wh must be chosen in such a way to obtain a
CFxDEN greater than 1. Fractional results cannot be
accommodated by the frequency converter, so the result of the
division has to be rounded to the nearest integer. If CFxDEN is
set equal to 0, then the ADE7854 considers it as equal to 1.
The pulse output for all digital to frequency converters stays low
for 80ms if the pulse period is larger than 160ms (6.25Hz). If
the pulse period is smaller than 160ms, the duty cycle of the
pulse output is 50%. The pulse output is active low and should
be preferably connected to an LED as shown in Figure 52.
Bits 11, 10, 9 (CF3DIS , CF2DIS and CF1DIS) of
CFMODE[15:0] register decide if the frequency converter
output is generated at CF3, CF2 or CF1 pins. When bit CFxDIS,
x=1, 2, 3 is set to 1, the default value, the CFx pin is disabled
and the pin stays high. When bit CFxDIS is cleared to 0, the
correspondent CFx pin output generates an active low signal.
Bits 16, 15, 14 (CF3, CF2, CF1) in interrupt mask register
MASK0[31:0] manage CF3, CF2 and CF1 related interrupts.
When CFx, x=1, 2, 3 bits are set, whenever a high to low
CFxDEN
=
Description
CFx signal proportional to the sum of total phase active powers
Reserved
CFx signal proportional to the sum of phase apparent powers
Reserved
MC
[
imp
10
/
kwh
3
]
⋅
10
n
n
wh], n a positive or negative
(32)
Rev. PrC| Page 42 of 71
powers and CF3 produces signals proportional to apparent
powers. CF2 digital to frequency converter does not produce a
signal as its default setting is reserved.
transition at corresponding frequency converter output occurs,
an interrupt
STATUS0[31:0] register is set to 1. The interrupt is available
even if the CFx output is not enabled by CFxDIS bits in
CFMODE[15:0].
Synchronizing energy registers with CFx outputs
The ADE7854 contains a feature that allows synchronizing the
content of phase energy accumulation registers with the
generation of a CFx pulse. When a high to low transition at one
frequency converter output occurs, the content of all internal
phase energy registers that relate to the power being output at
CFx pin is latched into hr registers and then is reset to 0. See
Table 16 for the list of registers that are latched based on
CFxSEL[2:0] bits in CFMODE[15:0] register. All 3 phase
registers are latched independent of TERMSELx bits of
COMPMODE[15:0] register. The process is shown in Figure 53
for CF1SEL[2:0]=010 (apparent powers contribute at CF1 pin)
and CFCYC=2.
CFCYC[7:0] 8-bit unsigned register contains the number of
high to low transitions at frequency converter output between
two consecutive latches. Writing a new value into CFCYC[7:0]
register during a high to low transition at any CFx pin should be
avoided.
CF1 pulse based on
phase A and phase
B apparent powers
Figure 53.Synchronizing AVAHR and BVAHR with CF1
AVAHR, BVAHR, CVAHR latched
IRQ is triggered and a status bit in
Figure 52. CF pin recommended connection
Energy registers reset
0
CFx pin
Registers latched when CFxLATCH=1
AWATTHR, BWATTHR, CWATTHR
AVAHR, BVAHR, CVAHR
Preliminary Technical Data
V
CFCYC=2
DD
AVAHR, BVAHR, CVAHR latched
Energy registers reset