ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 31

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
REFERENCE CIRCUIT
The nominal reference voltage at the REF
This is the reference voltage used for the ADCs in the
ADE7854. The REF
source, for example, an external 1.2 V reference. The voltage of
the ADE7854 reference drifts slightly with temperature; see the
Specifications section for the temperature coefficient
specification (in ppm/°C). The value of the temperature drift varies
from part to part. Because the reference is used for all ADCs,
any x% drift in the reference results in a 2x% deviation of the
meter accuracy. The reference drift resulting from temperature
changes is usually very small and typically much smaller than
the drift of other components on a meter. Alternatively, the meter
can be calibrated at multiple temperatures.
If bit 0 (EXTREFEN) in CONFIG2[7:0] register is cleared to 0
(the default value), the ADE7854 use the internal voltage
reference. If the bit is set to 1, then the external voltage
reference is used. CONFIG2 register should be set during PSM0
mode. Its value is maintained during the other power mode
PSM3.
IN/OUT
IA
VA
VA
IA
VAP
pin can be overdriven by an external
IAP
IAN
VN
50Hz
PGA3
PGA1
° 1
IN/OUT
pin is 1.2±1% V.
Figure 38. Phase Calibration on Voltage Channels
Rev. PrC| Page 31 of 71
ADC
ADC
DIGITAL SIGNAL PROCESSOR
The ADE7854 contains an internal Digital Signal Processor
(DSP) that computes all powers and rms values. It contains
various memories: program memory ROM, program memory
RAM, data memory RAM.
The program used for the power and rms computations is
stored in the program memory ROM and the processor
executes it every 8KHz. The end of the computations is signaled
by setting bit 17 (DREADY) to 1 in STATUS0[31:0] register. An
interrupt attached to this flag may be enabled by setting bit 17
(DREADY) in MASK0[31:0] register. If enabled, the
is set low and status bit DREADY is set to 1 at the end of the
computations. The status bit is cleared and
high by writing STATUS0[31:0] register with bit 17 (DREADY)
set to 1.
The registers used by the DSP are located in the data memory
RAM, at addresses between 0x4000 and 0x43FF. The width of
this memory is 28 bits.
As seen in Power Up Procedure section, at power up or after a
hardware or software reset, the DSP is in idle mode. No
instruction is being executed. All the registers located in the
data memory RAM are initialized at 0, their default values. The
register RUN[15:0] used to start and stop the DSP is cleared to
IA
VA
APHCAL=57
Calibration
Phase compensation achieved
Phase
delaying IA by 56us
IRQ pin is set back
0
ADE7854
IRQ pin
0