ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 63

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
Location
13
14
15
16
17
18
19
20-22
23
24
31:25
Table 30. PHSTATUS register (address 0xE600)
Bit Location
2-0
3
4
5
8-6
9
10
11
12
13
14
15
Table 31. PHNOLOAD register (address 0xE608)
Bit
Location
0
1
2
3-5
6
7
8
Bit
Mnemonic
ZXIB
ZXIC
RSTDONE
SAG
OI
OV
SEQERR
Reserved
PKI
PKV
Bit
Mnemonic
NLPHASE[0]
NLPHASE[1]
NLPHASE[2]
Reserved
VANLPHASE[0]
VANLPHASE[1]
VANLPHASE[2]
Bit Mnemonic
OIPHASE[0]
OIPHASE[1]
OIPHASE[1]
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
VSPHASE[1]
VSPHASE[2]
Default
value
0
0
0
0
0
0
0
000
0
0
000 0000
Default
value
0
0
0
000
0
0
0
Default value
000
0
0
0
000
0
0
0
0
0
0
0
Description
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase B current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase C current.
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the phases
indicated by bits 14-12 (VSPHASE) in PHSTATUS[15:0] register (see Table 30).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of the
phases indicated by bits 5-3 (OIPHASE) in PHSTATUS[15:0] register (see Table 30).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of the
phases indicated by bits 11-9 (OVPHASE) in PHSTATUS[15:0] register (see Table 30).
When this bit is set to 1, it enables an interrupt when a negative to positive zero crossing on phase
A voltage is not followed by a negative to positive zero crossing on phase B voltage, but by a
negative to positive zero crossing on phase C voltage.
These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in
the current channel has ended.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in
the voltage channel has ended.
These bits do not manage any functionality.
Description
-0: phase A is out of no-load condition based on total active powers.
-1: phase A is in no load condition based on total active powers. Bit set together with bit 0
(NLOAD) in STATUS1[31:0].
-0: phase B is out of no-load condition based on total active powers.
-1: phase B is in no load condition based on total active powers. Bit set together with bit 0
(NLOAD) in STATUS1[31:0].
-0: phase C is out of no-load condition based on total active powers.
-1: phase C is in no load condition based on total active powers. Bit set together with bit 0
(NLOAD) in STATUS1[31:0].
These bits are always 0.
-0: phase A is out of no-load condition based on apparent power.
-1: phase A is in no load condition based on apparent power. Bit set together with bit 2
(VANLOAD) in STATUS1[31:0].
-0: phase B is out of no-load condition based on apparent power.
-1: phase B is in no load condition based on apparent power. Bit set together with bit 2
(VANLOAD) in STATUS1[31:0].
-0: phase C is out of no-load condition based on apparent power.
-1: phase C is in no load condition based on apparent power. Bit set together with bit 2
Description
These bits are always 0.
When this bit is set to 1, phase A current generated bit 17 (OI) in STATUS1[31:0]
When this bit is set to 1, phase B current generated bit 17 (OI) in STATUS1[31:0]
When this bit is set to 1, phase C current generated bit 17 (OI) in STATUS1[31:0]
These bits are always 0.
When this bit is set to 1, phase A voltage generated bit 18 (OV) in STATUS1[31:0]
When this bit is set to 1, phase B voltage generated bit 18 (OV) in STATUS1[31:0]
When this bit is set to 1, phase C voltage generated bit 18 (OV) in STATUS1[31:0]
When this bit is set to 1, phase A voltage generated bit 16 (SAG) in STATUS1[31:0]
When this bit is set to 1, phase B voltage generated 16 (SAG) in STATUS1[31:0]
When this bit is set to 1, phase C voltage generated 16 (SAG) in STATUS1[31:0]
This bit is always 0.
Rev. PrC| Page 63 of 71
ADE7854