ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 52

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
for HXFER[1:0] is reserved and writing it is equivalent to
writing 00, the default value.
Bit 5 (HSAPOL) determines the polarity of HSA pin during the
communication. When HSAPOL is 0, the default value, the
HSA pin is active low during the communication. This means
that HSA stays high when no communication is in progress.
When the communication starts, HSA goes low and stays low
until the communication ends. Then it goes back high. When
HSAPOL is 1, the HSA pin is active high during the
communication. This means that HSA stays low when no
communication is in progress. When the communication starts,
HSA goes high and stays high until the communication ends.
Then it goes back low.
Bits 7, 6 of HSDC_CFG are reserved. Any value written into
these bits does not have any consequence on HSDC behavior.
Figure 67 shows the HSDC transfer protocol for HGAP=0,
HXFER[1:0]=00 and HSAPOL=0. Note that the HSDC
interface sets a bit on HSD line every HSCLK high to low
transition and the value of bit HSIZE is irrelevant.
Figure 68 shows the HSDC transfer protocol for HSIZE=0,
HGAP=1, HXFER[1:0]=00 and HSAPOL=0. Note that HSDC
interface introduces a 7 HSCLK cycles gap between every 32-bit
word.
Figure 69 shows the HSDC transfer protocol for HSIZE=1,
HGAP=1, HXFER[1:0]=00 and HSAPOL=0. Note that HSDC
interface introduces a 7 HSCLK cycles gap between every 8-bit
word.
HSCLK
HSD
HSA
31
IAVW (32bit)
Figure 67. HSDC communication for HGAP=0, HXFER[1:0]=00 and HSAPOL=0. HSIZE is irrelevant
0
31
IBWV(32bit)
Rev. PrC| Page 52 of 71
0
31
ICWV(32bit)
Table 18 presents the time it takes to execute an HSDC data
transfer for all HSDC_CFG[7:0] settings. For some settings, the
transfer time is less than 125usec (8KHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125usec, the HSDC port transmits data only in the
first of two consecutive 8KHz sampling cycles. This means it
transmits registers at an effective rate of 4KHz.
Table 18. Communication times for various HSDC settings
HXFER[1:0]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
0
HGAP
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
Preliminary Technical Data
HSIZE
*
*
0
0
1
1
*
*
0
0
1
1
*
*
0
0
1
1
HCLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
31
CVA(32bit)
Comm Time [μsec]
64
128
77.125
154.25
119.25
238.25
28
56
33.25
66.5
51.625
103.25
36
72
43
86
66.625
133.25
0