ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 17

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
As the ADE7854 enters PSM0 mode, the I
serial port. If the SPI port is used, then the SS pin must be
toggled three times high to low. This action selects the
ADE7854 into using the SPI port for further use. If I
active serial port, bit 1 (I2C_LOCK) of CONFIG2[7:0] must be
set to 1 to lock it in. From this moment on, the ADE7854
ignores spurious togglings of the SS pin and an eventual switch
into using SPI port is no longer possible. If SPI is the active
serial port, any write to CONFIG2[7:0] registers locks the port.
From this moment on, a switch into using I
possible.
Only a power down or setting RESET pin low resets back the
ADE7854 to use the I
choice is maintained when the ADE7854 changes between
PSM0 and PSM3 power modes.
Immediately after entering PSM0, the ADE7854 sets all registers
to their default values, including LPOILVL[7:0] and
CONFIG2[7:0]. The ADE7854 signals the end of the transition
period by triggering
(RSTDONE) in STATUS1[31:0] register to 1. This bit is 0
during the transition period and becomes 1 when the transition
ends. The status bit is cleared and
writing STATUS1[31:0] register with the corresponding bit set
to 1. As the RSTDONE is an unmaskable interrupt, bit 15
(RSTDONE) in STATUS1[31:0] register has to be cancelled in
order for the
wait until
register to test the state of RSTDONE bit. As a good
programming practice, it is also recommended at this point to
cancel all other status flags in STATUS1[31:0] and
STATUS0[31:0] registers by writing the corresponding bits with
1.
Initially, the DSP is in idle mode, which means it does not
execute any instruction. This is the moment to initialize all
ADE7854 registers and then write 0x0001 into the RUN[15:0]
register to start the DSP (see Digital Signal Processor chapter
for details on the RUN[15:0] register).
If the supply voltage VDD becomes lower than 2V ± 10%, the
ADE7854 goes into inactive state, which means no
measurements are executed.
Hardware Reset
The ADE7854 has a RESET pin. If the ADE7854 is in PSM0
mode and RESET pin is set low, then the ADE7854 enters in
hardware reset state. The ADE7854 has to be in PSM0 mode for
hardware reset to be considered. Setting RESET pin low while
the ADE7854 is in PSM3 mode does not have any effect.
Table 8: ADE7854 Power modes and related characteristics
Power
Mode
PSM0
IRQ pin goes low before accessing STATUS1[31:0]
State after
hardware reset
IRQ pin to turn back high. It is recommended to
1
1
IRQ interrupt pin low and setting bit 15
2
C port. Once locked, the serial port
1
Registers
Set to
default
IRQ pin is set back high by
1
2
C port is the active
2
C port is no longer
LPOILVL, CONFIG2
Set to default
2
C is the
Rev. PrC| Page 17 of 71
I
I
2
2
C enabled
C/SPI
from high to low and then back high, all the registers are set to
their default values, including LPOILVL[7:0] and
CONFIG2[7:0]. The ADE7854 signals the end of the transition
period by triggering
(RSTDONE) in STATUS1[31:0] register to 1. This bit is 0
during the transition period and becomes 1 when the transition
ends. The status bit is cleared and
writing STATUS1[31:0] register with the corresponding bit set
to 1.
does not execute any instruction. As the I
serial port of the ADE7854, it becomes active after a reset state.
If SPI is the port used by the external microprocessor, the
procedure to enable it has to be repeated immediately after
for details.
At this point, it is recommended to initialize all ADE7854
registers and then write 0x0001 into the RUN[15:0] register to
start the DSP (see Digital Signal Processor chapter for details on
RUN[15:0] register).
Software Reset Functionality
Bit 7 (SWRST) in CONFIG[15:0] register manages the software
reset functionality in PSM0 mode. The default value of this bit
is 0. If this bit is set to 1, then the ADE7854 enters a software
reset state. In this state, almost all internal registers are set to
their default value. In addition, the choice of what serial port
I
has been previously executed (See Serial Interfaces chapter for
details). The registers that maintain their values despite SWRST
bit being set to 1 are LPOILVL[7:0] and CONFIG2[7:0]. When
the software reset ends, bit 7 (SWRST) in CONFIG[15:0] is
cleared to 0, the
(RSTDONE) in STATUS1[31:0] register is set to 1. This bit is 0
during the transition period and becomes 1 when the transition
ends. The status bit is cleared and
writing STATUS1[31:0] register with the corresponding bit set
to 1.
After a software reset ended, the DSP is in idle mode, which
means it does not execute any instruction. It is recommended to
initialize all the ADE7854 registers and then write 0x0001 into
the RUN[15:0] register to start the DSP (see Digital Signal
Processor chapter for details on the RUN[15:0] register).
Software reset functionality is not available in PSM3 mode.
RESET pin is toggled back high. See Serial Interfaces chapter
If the ADE7854 is in PSM0 mode and RESET pin is toggled
After a hardware reset, the DSP is in idle mode, which means it
2
C or SPI is in use remains unchanged if the lock in procedure
IRQ interrupt pin is set low and bit 15
1
IRQ interrupt pin low and setting bit 15
1
Functionality
All circuits are active. DSP is in
idle mode
IRQ pin is set back high by
IRQ pin is set back high by
1
1
2
C port is the default
ADE7854