ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 54

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
REGISTERS LIST
Table 19. ADE7854 Registers List located in DSP data memory RAM
Address
0x4380
0x4381
0x4382
0x4383
0x4384
0x4385
0x4386
0x4387
0x4388
0x4389
0x438A
0x438B
0x438C
0x438D
0x438E
0x438F
0x4390
0x4391
0x4392
0x4393
0x4394
0x4395
0x4396
0x4397-
0x43A8
0x43A9
0x43AA
0x43AB
0x43AC
0x43AD-
0x43AF
0x43B0
0x43B1
0x43B2
0x43B3-
0x43B4
0x43B5
0x43B6
Name
AIGAIN
AVGAIN
BIGAIN
BVGAIN
CIGAIN
CVGAIN
Reserved
AIRMSOS
AVRMSOS
BIRMSOS
BVRMSOS
CIRMSOS
CVRMSOS
reserved
AVAGAIN
BVAGAIN
CVAGAIN
AWGAIN
AWATTOS
BWGAIN
BWATTOS
CWGAIN
CWATTOS
reserved
VATHR1
VATHR0
WTHR1
WTHR0
reserved
VANOLOAD
APNOLOAD
VARNOLOAD
reserved
DICOEFF
HPFDIS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
24
24
Bit
Length
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
Bit Length
during
Comm
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZP
32 ZP
32 ZP
32 ZP
32 ZPSE
32 ZPSE
32 ZPSE
32ZPSE
32 ZP
2
Rev. PrC| Page 54 of 71
Type
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
U
U
U
U
S
S
S
S
U
3
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Default
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x0000000
Description
Phase A current gain adjust
Phase A voltage gain adjust
Phase B current gain adjust
Phase B voltage gain adjust
Phase C current gain adjust
Phase C voltage gain adjust
This memory location should be kept at 0x000000
for proper operation
Phase A current rms offset
Phase A voltage rms offset
Phase B current rms offset
Phase B voltage rms offset
Phase C current rms offset
Phase C voltage rms offset
This memory location should be kept at 0x000000
for proper operation
Phase A apparent power gain adjust
Phase B apparent power gain adjust
Phase C apparent power gain adjust
Phase A total active power gain adjust
Phase A total active power offset adjust
Phase B total active power gain adjust
Phase B total active power offset adjust
Phase C total active power gain adjust
Phase C total active power offset adjust
These memory locations should be kept at
0x000000 for proper operation
Most significant 24 bits of VATHR[47:0] threshold
used in phase apparent power data path.
Less significant 24 bits of VATHR[47:0] threshold
used in phase apparent power data path.
Most significant 24 bits of WTHR[47:0] threshold
used in phase total active power data path.
Less significant 24 bits of WTHR[47:0] threshold
used in phase total active power data path.
This memory location should be kept at 0x000000
for proper operation
No-load threshold in the apparent power data path
No-load threshold in the total active power data
path
This register must be set at 0x800000 to ensure the
correct functionality of no-load detection circuit
based on total active power (See No-load detection
based on total active power section for details).
This memory location should not be written for
proper operation
Register used in the digital integrator algorithm. If
the integrator is turned on, it must be set at
0xFF8000
Disables/enables the HPF in the current data path.
(Table 23 )
Preliminary Technical Data