ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 37

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Setting bit 0 in MASK0[31:0] register enables the AEHF
interrupts. If enabled, the
is set to 1 whenever one of the energy registers xWATTHR (for
AEHF interrupt), x=A, B, C becomes half full. The status bit is
cleared and
register with the corresponding bit set to 1.
Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a
read-with-reset for all watt-hr accumulation registers, that is,
the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation
register is 125μs (1/8KHz). With full-scale sinusoidal signals on
the analog inputs and the watt gain registers set to 0x00000, the
average word value from each LPF2 is
PMAX=33,516,139=0x1FF6A6B. If the WTHR[47:0] threshold
is set at PMAX level, this means the DSP generates a pulse that
is added at watt-hr registers every 125 μs.
The maximum value that can be stored in the watt-hr
accumulation register before it overflows is 2
0x7FFFFFFF. The integration time is calculated as
Energy Accumulation Modes
The active power accumulated in each watt-hr accumulation
32-bit register (AWATTHR, BWATTHR, CWATTHR) depends
on the configuration of bits 5, 4 (CONSEL) in ACCMODE[7:0]
register. The different configurations are described in Table 12.
Table 12. Inputs to Watt-Hr Accumulation Registers
CONSEL
00
01
10
11
Depending on the poly-phase meter service, the appropriate
formula should be chosen to calculate the active energy. The
American ANSI C12.10 Standard defines the different
configurations of the meter. Table 13 describes which mode
should be chosen in these different configurations.
Table 13. Meter Form Configuration
ANSI Meter Form
5S/13S
6S/14S
8S/15S
9S/16S
Bits 1, 0 (WATTACC[1:0]) in ACCMODE[7:0] register
determine how CF frequency output may be generated function
of the total and fundamental active powers. While the watt-hr
accumulation registers accumulate the active power in a signed
format, the frequency output may be generated in signed mode
Time
=
0
7 x
AWATTHR
VA × IA
VA × IA
VA × IA
VA × IA
FFF
IRQ pin is set to logic high by writing STATUS0
,
0
FFFF
3-Wire Delta
4-Wire Wye
4-Wire Delta
4-Wire Wye
×
125
IRQ pin is set low and the status bit
μ
s
BWATTHR
VB × IB
0
VB × IB
VB = −VA − VC
VB × IB
VB = −VA
=
0
74
h
33
min
55
31
s
CONSEL
01
10
11
00
− 1 or
CWATTHR
VC × IC
VC × IC
VC × IC
VC × IC
(23)
Rev. PrC| Page 37 of 71
or in absolute mode, function of WATTACC[1:0]. See
ENERGY to FREQUENCY CONVERSION chapter for details.
Line Cycle Active Energy Accumulation Mode
In line cycle energy accumulation mode, the energy accumula-
tion is synchronized to the voltage channel zero crossings so
that active energy is accumulated over an integral number of
half line cycles. The advantage of summing the active energy
over an integer number of line cycles is that the sinusoidal
component in the active energy is reduced to 0. This eliminates
any ripple in the energy calculation and allows the energy to be
accumulated accurately over a shorter time. By using the line
cycle energy accumulation mode, the energy calibration can be
greatly simplified, and the time required to calibrate the meter
can be significantly reduced. In line cycle energy accumulation
mode, the ADE7854 transfers the active energy accumulated in
the 32-bit internal accumulation registers into
xWATHHR[31:0], x=A,B,C registers after an integral number of
line cycles, as shown in Figure 48. The number of half line
cycles is specified in the LINECYC[15:0] register.
The line cycle energy accumulation mode is activated by setting
bit 0 (LWATT) in the LCYCMODE[7:0] register. The energy
accumulation over an integer number of half line cycles is
written to the watt-hr accumulation registers after
LINECYC[15:0] number of half line cycles are detected. When
using the line cycle accumulation mode, the bit 6 (RSTREAD) of
the LCYCMODE[7:0] register should be set to Logic 0 because
the read with reset of watt-hr registers is not available in this
mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half-line cycles by
setting bits 5, 4, 3 (ZXSEL) in the LCYCMODE[7:0] register.
Any combination of the zero crossings from all three phases can
be used for counting the zero crossing. Only one phase should
be selected at a time for inclusion in the zero crossings count
during line accumulation.
FROM LPF2
OUTPUT
ZERO CROSSING
ZERO CROSSING
ZERO CROSSING
DETECTION
DETECTION
DETECTION
(PHASE A)
(PHASE B)
(PHASE C)
Figure 48. ADE7854 Line Cycle Active Energy Accumulation Mode
LCYCMODE[7:0]
LCYCMODE[7:0]
LCYCMODE[7:0]
AWATTOS
ZXSEL[0] in
ZXSEL[1] in
ZXSEL[2] in
Σ
AWGAIN
Σ
WTHR[47:0]
56 bits
LINECYC[15:0]
CALIBRATION
CONTROL
Σ
AWATTHR[31:0]
ADE7854
32 bit register