ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 47

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SERIAL INTERFACES
The ADE7854 has three serial port interfaces: one fully licensed
I
Speed Data Capture Port (HSDC). As the SPI pins are
multiplexed with some of the pins of I
ADE7854 accepts two configurations: one using SPI port only
and one using I
Serial interface choice
After reset, the HSDC port is always disabled. The choice
between I
after power up or after a hardware reset. If SS pin is kept high,
then ADE7854 will use the I
is executed. If SS pin is toggled high low 3 times after power up
or after a hardware reset, then the ADE7854 will use the SPI
port until a new hardware reset is executed. This manipulation
of the SS pin can be accomplished in two ways: one way is to
use the SS pin of the master device (i.e. the microcontroller) as
a regular I/O pin and toggle it 3 times. Another way is to
execute 3 SPI write operations to a location in the address space
that is not allocated to a specific ADE7854 register (for example
0xEBFF). These writes allow the SS pin to toggle 3 times. See
SPI Write Operation section for details on the write protocol
involved.
After the serial port choice is done, it needs to be locked, so the
active port remains in use until a hardware reset is executed in
PSM0 normal mode or until a power down. If I
serial port, bit 1 (I2C_LOCK) of CONFIG2[7:0] must be set to
1 to lock it in. From this moment on, the ADE7854 ignores
spurious togglings of the SS pin and an eventual switch into
using SPI port is no longer possible. If SPI is the active serial
port, any write to CONFIG2[7:0] register locks the port. From
this moment on, a switch into using I
possible.
Once locked, the serial port choice is maintained when the
ADE7854 changes between PSM0 and PSM3 power modes.
The functionality of the ADE7854 is accessible via several on-
chip registers. The contents of these registers can be updated or
read using the I
state of up to 13 registers representing instantaneous values of
phase voltages and currents, neutral current, active and
apparent powers.
2
SEQUENCE
PROGRAM
C interface, one Serial Peripheral Interface (SPI) and one High
IRQx
2
C and SPI port is done by manipulating the SS pin
2
2
C port in conjunction with HSDC port.
t
C or SPI interfaces. HSDC port provides the
1
to ISR
JUMP
Figure 59. ADE7854 interrupt management when PHSTATUS, IPEAK, VPEAK or PHSIGN registers are involved
INTERRUPT
GLOBAL
MASK
2
C port until a new hardware reset
CLEAR MCU
INTERRUPT
2
2
C port is no longer
C and HSDC ports, the
FLAG
2
C is the active
STATUSx
READ
Rev. PrC| Page 47 of 71
READ
PHx
STATUSx
WRITE
BACK
I
The ADE7854 supports a fully licensed I
interface is implemented as a full hardware slave. SDA is the
data I/O pin, and SCL is the serial clock. These two pins are
shared with the MOSI and SCLK pins of the on-chip SPI
interface. The maximum serial clock frequency supported by
this interface is 400KHz.
The two pins used for data transfer, SDA and SCL are
configured in a Wired-AND format that allows arbitration in a
multi-master system.
The transfer sequence of an I
device initiating a transfer by generating a START condition
while the bus is idle. The master transmits the address of the
slave device and the direction of the data transfer in the initial
address transfer. If the slave acknowledges, then the data
transfer is initiated. This continues until the master issues a
STOP condition and the bus becomes idle.
I
The write operation using I
initiates when the master generates a START condition and
consists in one byte representing the address of the ADE7854
followed by the 16-bit address of the target register and by the
value of the register.
The most significant 7 bits of the address byte constitute the
address of the ADE7854 and they are equal to b#0111000. Bit 0
of the address byte is READ/ WRITE bit. Because this is a write
operation, it has to cleared to 0, so the first byte of the write
operation is 0x70. After every byte is received, the ADE7854
generates an acknowledge. As registers may have 8, 16 or 32
bits, after the last bit of the register is transmitted and the
ADE7854 acknowledges the transfer, the master generates a
STOP condition. The addresses and the register content are
sent with the most significant bit first. See Figure 60 for details
of the I
I
The read operation using the I
done in two stages. The first stage sets the pointer to the address
of the register. The second stage reads the content of the
register.
As seen in Figure 61, the first stage initiates when the master
generates a START condition and consists in one byte
representing the address of the ADE7854 followed by the 16-bit
address of the target register. The ADE7854 acknowledges every
t
2
2
2
2
C Compatible Interface
C Write Operation
C Read Operation
(BASED ON STATUSx CONTENTS)
2
C write operation.
ISR ACTION
t
3
2
C interface of the ADE7854
2
C system consists of a master
2
C interface of the ADE7854 is
MCU INTERRUPT
GLOBAL INTERRUPT
FLAG SET
MASK RESET
ISR RETURN
2
C interface. The I
ADE7854
to ISR
JUMP
2
C