tspc106 ATMEL Corporation, tspc106 Datasheet - Page 10

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

60x Processor Interface Signals
Table 2. 60x Processor Interface Signals
10
Signal
A[0:31]
AACK
ARTRY
BG0
BR0
CI
DBG0
DBGLB
TSPC106A
Signal Name
Address bus
Address
acknowledge
Address retry
Bus grant 0
Bus request 0
Cache inhibit
Data bus grant 0
Local bus slave
data bus grant
Number of
Pins
32
1
1
1
1
1
1
1
I/O
I/O
O
O
O
O
O
O
I
I
I
I
Signal Description
Specifies the physical address for 60x bus snooping.
Specifies the physical address of the bus transaction. For burst reads,
the address is aligned to the critical double-word address that missed
in the instruction or data cache. For burst writes, the address is aligned
to the double-word address of the cache line being pushed from the
data cache.
Indicates that the address tenure of a transaction is terminated. On the
cycle following the assertion of AACK, the bus master releases the
address-tenure-related signals to a high impedance state and samples
ARTRY.
Indicates that an externally-controlled L2 cache is terminating the
address tenure. On the cycle following the assertion of AACK, the bus
master releases the address-tenure-related signals to a high
impedance state and samples ARTRY.
Indicates that the initiating 60x bus master must retry the current
address tenure.
During a snoop operation, indicates that the 60x either requires the
current address tenure to be retried due to a pipeline collision or needs
to perform a snoop copy-back operation. During normal 60x bus cycles
in a multiprocessor system, indicates that the other 60x or external L2
controller requires the address tenure to be retried.
Indicates that the primary 60x may, with the proper qualification, begin
a bus transaction and assume mastership of the address bus.
Indicates that the primary 60x requires the bus for a transaction.
Indicates that an access is caching-inhibited.
Indicates that the 60x may, with the proper qualification, assume
mastership of the data bus.
Indicates that the 60x processor is prepared to accept data and the
local bus slave should drive the data bus.
2102C–HIREL–01/05