tspc106 ATMEL Corporation, tspc106 Datasheet - Page 29

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Figure 10. Output Timing Diagram
Note:
Table 19. JTAG AC Timing Specifications (Independent of SYSCLK) (V
-55°C ≤ T
Notes:
2102C–HIREL–01/05
Ref
10
11
12
13
All Outputs
(except TS and ARTRY)
1
2
3
4
5
6
7
8
9
SYSCLK
ARTRY
VM = Midpoint Voltage (1.4V)
1. These values are guaranteed by design, and are not tested.
2. TRST is an asynchronous signal. The setup time is for test purposes only.
3. Non-test signal input timing with respect to TCK.
4. Non-test signal output timing with respect to TCK.
j
≤ 125°C)
Characteristic
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4 V
TCK rise and fall times
TRST setup time to TCK rising edge
TRST assert time
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
TCK to TDO high impedance
TS
12
13
VM
(3)
14
(3)
(2)
(1)
(2)
21
20
19
18
13
VM
15
16
DD
= 3.3V ± 5% dc, GND = 0V dc,C
Min
40
20
10
10
15
15
0
5
0
0
5
0
0
0
VM
15
16
Max
25
30
30
15
15
3
L
= 50 pF,
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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