tspc106 ATMEL Corporation, tspc106 Datasheet - Page 17

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Table 7. PCI Interface Signals
2102C–HIREL–01/05
Signal
PAR
PERR
PIRQ
REQ
SERR
STOP
TRDY
Signal Name
Parity
Parity error
Modified memory
interrupt request
PCI bus request
System error
Stop
Target ready
Number of
Pins
1
1
1
1
1
1
1
I/O
O
O
O
O
O
O
O
I
I
I
I
I
Signal Description
Asserted indicates odd parity across the AD[31:0] and C/BE[3:0]
signals during address and data phases. Negated indicates even
parity.
Asserted indicates odd parity driven by another PCI master or the PCI
target during read data phases. Negated indicates even parity.
Indicates that another PCI agent detected a data parity error.
Indicates that another PCI agent detected a data parity error.
In emulation mode (see “Address Maps” on page 19), indicates that a
PCI write has occurred to system memory that has not been recorded
by software.
Indicates that the TSPC106 is requesting control of the PCI bus to
perform a transaction. Note that REQ is a point-to-point signal. Every
master has its own REQ signal.
Indicates that an address parity error or some other system error
(where the result will be a catastrophic error) was detected.
Indicates that another target has detected a catastrophic error.
Indicates that the TSPC106, acting as the PCI target, is requesting that
the PCI bus master stop the current transaction.
Indicates that some other PCI agent is requesting that the PCI initiator
stop the current transaction.
Indicates that the TSPC106, acting as a PCI target, can complete the
current data phase of a PCI transaction. During a read, the TSPC106
asserts TRDY to indicate that valid data is present on AD[31:0]. During
a write, the TSPC106 asserts TRDY to indicate that it is prepared to
accept data.
Indicates that another PCI target is able to complete the current data
phase of a transaction.
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