tspc106 ATMEL Corporation, tspc106 Datasheet - Page 13

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Table 3. Internal L2 Controller Signals (Continued)
External L2 Controller Signals When an external L2 cache controller is used instead of the internal L2 cache controller,
Table 4. External L2 Controller Signals
2102C–HIREL–01/05
Signal
DOE
DBGL2
DWE[0:2]
DBG2
DBG3
HIT
TOE
DBG1
TV
BR2
TWE
BG2
Signal
BGL2
BA1
BAA
BRL2
ADS
DALE
DBGL2
DOE
HIT
Signal Name
External L2 bus
grant
External L2 bus
request
External L2 data
bus grant
External L2 hit
Signal Name
Data RAM output
enable
Data RAM write
enable
Hit
Tag output enable
Tag valid
Tag write enable
four signals change their functions.
Number of
Number of
Pins
Pins
1
1
1
1
1
3
1
1
1
1
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
Signal Description
Indicates that the external L2 controller has been granted mastership
of the 60x address bus
Indicates that the external L2 controller requires mastership of the 60x
bus for a transaction
Indicates that the external L2 controller has been granted mastership
of the 60x data bus
Indicates that the current transaction is claimed by the external L2
controller. The external L2 controller will assert AACK and TA for the
transaction
Signal Description
Indicates that the L2 data RAMs should drive the data bus
Indicates that a write to the L2 data RAMs is in progress. Multiple pins
are provided to reduce loading
Indicates that the L2 cache has detected a hit. The polarity of HIT is
programmable
Indicates that the tag RAM should drive the L2 tag address onto the
address bus.
Indicates that the current L2 cache line should be marked valid. The
polarity of TV is programmable
Indicates that the L2 tag address, valid, and dirty bits should be
updated
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