tspc106 ATMEL Corporation, tspc106 Datasheet - Page 18

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Interrupt, Clock and Power Management Signals
The TSPC106 coordinates interrupt, clocking, and power management signals across the memory bus, the PCI bus and
the 60x processor bus.
Table 8. Interrupt, Clock and Power Management Signals
IEEE 1149.1 Interface Signals
To facilitate system testing, the TSPC106 provides a JTAG test access port that complies with the IEEE 1149.1 boundary-
scan specification.
Table 9. IEEE 1149.1 Interface Signals
18
Signal
CKO
DWE2
HRST
NMI
QACK
QREQ
SUSPEND
SYSCLK
Signal
TCK
TDO
TDI
TMS
TRST
TSPC106A
Signal Name
Test clock
Hard reset
Nonmaskable
interrupt
Quiesce
acknowledge
Quiesce request
Suspend
System clock
Signal Name
JTAG test clock
JTAG test data
output
JTAG test data
input
JTAG test mode
select
JTAG test reset
Number of
Number of
Pins
Pins
1
1
1
1
1
1
1
1
1
1
1
1
I/O
I/O
O
O
O
I
I
I
I
I
I
I
I
I
Signal Description
CKO provides a means to monitor the internal PLL output or the bus clock
frequency. The CKO clock should be used for testing purposes only. It is not
intended as a reference clock signal.
Initiates a complete hard reset of the TSPC106. During assertion, all bi-
directional signals are released to a high-impedance state and all output signals
are either in a high impedance or inactive state.
Indicates that an external device (typically an interrupt controller) has detected a
catastrophic error. In response, the TSPC106 asserts MCP on the 60x
processor bus.
Indicates that the TSPC106 is in a low-power state. All bus activity that requires
snooping has terminated and the 60x processor may enter a low-power state.
Indicates that a 60x processor is requesting that all bus activity involving snoop
operations pause or terminate so that the 60x processor may enter a low-power
state.
Activates the suspend power-saving mode.
SYSCLK sets the frequency of operation for the PCI bus and provides a
reference clock for the phase-locked loop (PLL) in the TSPC106. SYSCLK is
used to synchronize bus operations. Refer to section “Clocking” on page 19 for
more information.
Signal Description
Input signals to the test access port (TAP) are clocked in on the rising
edge of TCK. Changes to the TAP output signals occur on the falling
edge of TCK. The test logic allows TCK to be stopped.
The contents of the selected internal instructions or data register are
shifted out onto this signal on the falling edge of TCK. TDO will remain
in a high-impedance state except when scanning of data is in progress.
The value presented on this signal on the rising edge of TCK is clocked
into the selected JTAG test instruction or data register.
This signal is decoded by the internal JTAG TAP controller to
distinguish the primary operation of the test support circuitry.
This input causes asynchronous initialization of the internal JTAG TAP
controller.
2102C–HIREL–01/05