tspc106 ATMEL Corporation, tspc106 Datasheet - Page 25

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Dynamic Characteristics
Clock AC Specifications
Table 16. Clock AC Timing Specifications (V
Notes:
Figure 7. SYSCLK Input Timing Diagram
Note:
2102C–HIREL–01/05
Ref
2, 3
1
4
SYSCLK
1. The SYSCLK frequency and PLL[0:3] settings must be chosen so that the resulting SYSCLK (bus) frequency, CPU (core)
2. Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V.
3. Timing is guaranteed by design and characterization and is not tested.
4. The total input jitter (short-term and long-term combined) must be under ±200 ps.
5. PLL-relock time is the maximum time required for PLL lock after a stable V
VM = Midpoint Voltage (1.4V)
frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to
the PLL[0:3] signal description in “System Design Information” on page 33 for valid PLL[0:3] settings.
power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently reenabled dur-
ing the sleep and suspend power-saving modes. Also note that HRST must be held asserted for a minimum of 255 bus
clocks after the PLL-relock time (100 ms) during the power-on reset sequence.
Characteristic
60x processor bus (core) frequency
VCO frequency
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle measured at 1.4V
SYSCLK jitter
106 internal PLL relock time
(4)
(1)
VM
(1)
4
This section provides the AC electrical characteristics for the TSPC106. After fabrica-
tion, parts are sorted by maximum 60x processor bus frequency as shown in Table 16
and tested for conformance to the AC specifications for that frequency. These specifica-
tions are for operation between 16.67 and 33.33 MHz PCI bus (SYSCLK) frequencies.
The 60x processor bus frequency is determined by the PCI bus (SYSCLK) frequency
and the settings of the PLL[0:3] signals. All timings are specified relative to the rising
edge of SYSCLK.
Table 16 provides the clock AC timing specifications as defined in Figure 7.
(2)
(3, 5)
1
VM
(1)
DD
(3)
4
= 3.3V ± 5% dc, GND = 0V dc, -55°C ≤ T
SYSCLK/Core 33/66 MHz
16.67
16.67
30.0
Min
150
40
VM
CVIL
33.33
±200
Max
60.0
400
100
2.0
66
60
CVIH
DD
2
, AV
SYSCLK/Core 33/83.3 MHz
DD
16.67
16.67
30.0
, and SYSCLK are reached during the
Min
150
40
j
≤ 125°C)
33.33
±200
Max
83.3
60.0
400
2.0
100
60
3
MHz
MHz
MHz
Unit
ns
ns
ps
µs
%
25