tspc106 ATMEL Corporation, tspc106 Datasheet - Page 31

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Figure 14. Test Access Port Timing Diagram
Architectural
Overview
60x Processor Interface
Secondary (L2)
Cache/Multiple
Processor Interface
2102C–HIREL–01/05
TDI, TMS
TDO
TDO
TDO
TCK
The TSPC106 supports a programmable interface to a variety of PowerPC microproces-
sors operating at select bus speeds.The address bus is 32 bits wide and the data bus is
64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x bus
protocol, supporting single-beat and burst data transfers. The address and data buses
are decoupled to support pipelined transactions.
Two signals on the TSPC106, local bus slave claim (LBCLAIM) and data bus grant local
bus slave (DBGLB), are provided for an optional local bus slave. However, the local bus
slave must be capable of generating the transfer acknowledge (TA) signal to interact
with the 60x processor(s).
Depending on the system implementation, the processor bus may operate at the PCI
bus clock rate or at two or three times the PCI bus clock rate. The 60x processor bus is
synchronous with all timing relative to the rising edge of the 60x bus clock.
The 106 provides support for the following configurations of 60x processors and L2
cache:
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•
•
The internal L2 cache controller generates the arbitration and support signals necessary
to maintain a write-through or write-back L2 cache. The internal L2 cache controller sup-
ports either asynchronous SRAMs, pipelined burst SRAMs or synchronous burst
SRAMs, using byte parity for data error detection.
Up to four 60x processors with no L2 cache
A single 60x processor plus a direct-mapped, lookaside, L2 cache using the internal
L2 cache controller of the TSPC106
Up to four 60x processors plus an externally-controlled L2 cache
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12
Output Data Valid
Output Data Valid
Input Data Valid
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