tspc106 ATMEL Corporation, tspc106 Datasheet - Page 12

• Manufacturer Part Number: tspc106
• Description: Ic Pci Mem Ctrlr 66mhz 303cbga
• Manufacturer: ATMEL Corporation

Table 2. 60x Processor Interface Signals (Continued)
L2 Cache/Multiple
Processor Interface
Signals
Internal L2 Controller Signals
Table 3. Internal L2 Controller Signals
12
Signal
TSIZ[0:2]
TT[0:4]
WT
XATS
Signal
ADS
DALE
BRL2
BA0
BR3
BA1
BAA
BGL2
BAA
BA1
BGL2
DALE
ADS
BRL2
DCS
BG3
DIRTY_IN
BR1
DIRTY_OUT
BG1
TSPC106A
Signal Name
Transfer size
Transfer type
Write-through
Extended address
transfer start
Signal Name
Address strobe
Burst address 0
Burst address 1
Bus address
advance
Data address latch
enable
Data RAM chip
select
Dirty in
Dirty out
The TSPC106 provides support for either an internal L2 cache controller or an external
L2 cache controller and/or additional 60x processors.
Table 3 lists the interface signals for the internal L2 controller and provides a brief
description of their functions. The internal L2 controller supports either burst SRAMs or
asynchronous SRAMs. Some of the signals perform different functions depending on
the SRAM configuration.
Number of
Number of
Pins
Pins
3
5
1
1
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
Signal Description
For a burst SRAM configuration, indicates to the burst SRAM that the
address is valid to be latched
For an asynchronous SRAM configuration, indicates bit 0 of the burst
address counter
For an asynchronous SRAM configuration, indicates bit 1 of the burst
address counter
For a burst SRAM configuration, indicates that the burst RAMs should
increment their internal addresses
For an asynchronous SRAM configuration, indicates that the external
address latch should latch the current 60x bus address
Enables the L2 data RAMs for a read or write operation
Indicates that the selected L2 cache line is modified. The polarity of
DIRTY_IN is programmable
Indicates that the L2 cache line should be marked as modified. The
polarity of DIRTY_OUT is programmable
Signal Description
Specifies the data transfer size for the 60x bus transaction.
Specifies the data transfer size for the 60x bus transaction.
Specifies the type of 60x bus transfer in progress.
Specifies the type of 60x bus transfer in progress.
Indicates that an access is write-through.
Indicates that the 60x has started a direct-store access (using the
extended transfer protocol). Since direct-store accesses are not
supported by the TSPC106, the TSPC106 automatically asserts when
TEA and XATS are asserted (provided TEA is enabled).
2102C–HIREL–01/05