hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 177
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hd64338023s
Manufacturer Part Number
hd64338023s
Description
Renesas 8-bit Single-chip Microcomputer Super Low Power Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.HD64338023S.pdf
(697 pages)
- Current page: 177 of 697
- Download datasheet (6Mb)
5.6
5.6.1
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ
WKP
subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter,
SCI3, IRQAEC, IRQ
to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
5.6.2
Subactive mode is cleared by a SLEEP instruction or by a low input at the
• Clearing by SLEEP instruction
• Clearing by
5.6.3
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φ
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
Clearing by
5.3.2, Clearing Standby Mode.
W
0
/2, φ
interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode,
Transition to Subactive Mode
Clearing Subactive Mode
Operating Frequency in Subactive Mode
Subactive Mode
W
/4, and φ
R E S
R E S
pin
pin is the same as for standby mode; see Clearing by
4
W
, IRQ
/8.
3
, IRQ
1
, IRQ
0
, or WKP
7
to WKP
Rev. 7.00 Mar 10, 2005 page 135 of 652
0
interrupt is requested. A transition
Section 5 Power-Down Modes
R E S
R E S
pin in section
0
pin.
REJ09B0042-0700
, or WKP
7
to
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