hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 587

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

A.3
The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I • S
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2,
From table A.3:
S
Number of states required for execution = 2 • 2 + 2 • 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2,
From table A.3:
S
Number of states required for execution = 2 • 2 + 1 • 2+ 1 • 2 = 8
Table A.3
Execution Status
(instruction cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access
I
I
= 2,
= S
J
= S
J = K = 1,
for details.
S
Number of Execution States
K
L
= 2
J = K = M = N= 0
= 2
Number of Cycles in Each Instruction
L = M = N = 0
I
+ J • S
S
S
S
S
S
S
J
I
J
K
L
M
N
+ K • S
On-Chip Memory
2
1
K
+ L • S
L
+ M • S
Rev. 7.00 Mar 10, 2005 page 545 of 652
M
Access Location
+ N • S
On-Chip Peripheral Module
—
2 or 3 *
—
Appendix A CPU Instruction Set
N
REJ09B0042-0700