hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 361

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Event Counter Control/Status Register (ECCSR)
Bit
Initial Value
Read/Write
Note:
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
0
1
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
*
Bits 7 and 6 can only be written with 0, for flag clearing.
Description
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
R/W *
OVH
0
7
R/W *
OVL
0
6
R/W

0
5
CH2
R/W
4
0
Rev. 7.00 Mar 10, 2005 page 319 of 652
CUEH
R/W
0
3
CUEL
R/W
2
0
REJ09B0042-0700
CRCH
Section 9 Timers
R/W
0
1
(initial value)
CRCL
R/W
0
0