hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 366
hd64338023s
Manufacturer Part Number
hd64338023s
Description
Renesas 8-bit Single-chip Microcomputer Super Low Power Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.HD64338023S.pdf
(697 pages)
- Current page: 366 of 697
- Download datasheet (6Mb)
Section 9 Timers
8-bit Event Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and
with bits ALEGS1 and ALEGS0 when AEVL pin input is selected.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.21 shows an example of the software processing when ECH and ECL are used
as 8-bit event counters.
Start
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1,
AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.21. When the next clock is input after the ECH count value reaches
H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00,
and counting up is restarted. Similarly, when the next clock is input after the ECL count value
reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to
H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If
the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 7.00 Mar 10, 2005 page 324 of 652
REJ09B0042-0700
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