hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 182

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Power-Down Modes
4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
Example: Direct transition time = (2 + 1) • 8tw + (8192 + 14) • 16tosc = 24tw + 131296tosc
[Legend]
tosc:
tw:
tcyc:
tsubcyc: Subclock (φ
5.8.3
1. Direct transition from active (high-speed) mode to subactive mode
2. Direct transition from active (medium-speed) mode to subactive mode
3. Direct transition from subactive mode to active (high-speed) mode
4. Direct transition from subactive mode to active (medium-speed) mode
Rev. 7.00 Mar 10, 2005 page 140 of 652
REJ09B0042-0700
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
Notes on External Input Signal Changes before/after Direct Transition
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
(when φw/8 or φ/8 is selected as the CPU operating clock, and wait time = 8192 states)
SUB
processing states) } • (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } • (tcyc after transition)
) cycle time
........................ (4)