m58bw32f STMicroelectronics, m58bw32f Datasheet

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m58bw32f

Manufacturer Part Number
m58bw32f
Description
16 Or 32 Mbit X32, Boot Block, Burst 3.3v Supply Flash Memories
Manufacturer
STMicroelectronics
Datasheet

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Features
January 2008
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Supply voltage
– V
– V
High performance
– Access times: 45 and 55 ns
– Synchronous burst reads
– 75 MHz effective zero wait-state burst read
– Asynchronous page reads
M58BW32F memory organization:
– Eight 64 Kbit small parameter blocks
– Four 128 Kbit large parameter blocks
– Sixty-two 512 Kbit main blocks
M58BW16F memory organization:
– Eight 64 Kbit parameter blocks
– Thirty-one 512 Kbit main blocks
Hardware block protection
– WP pin to protect any block combination
– PEN signal for Program/Erase Enable
Irreversible modify protection (OTP like) on
128 Kbits:
– Block 1 (bottom device) or block 72 (top
– Blocks 2 and 3 (bottom device) or blocks 36
Security
– 64-bit unique device identifier (UID)
Fast programming
– Write to buffer and program capability
Optimized for FDI drivers
– Common Flash interface (CFI)
– Fast Program/Erase Suspend feature in
Low power consumption
V
buffers
from Program and Erase operations
device) in the M58BW32F
and 35 (top device) in the M58BW16F
each block
DD
DD
DDQ
= 2.7 V to 3.6 V (45 ns) or
= 2.5 V to 3.3 V (55 ns)
= V
DDQIN
= 2.4 V to 3.6 V for I/O
16 or 32 Mbit (x 32, boot block, burst)
Rev 4
– 100 µA typical Standby current
Electronic signature
– Manufacturer code: 0020h
– Top device codes:
– Bottom device codes:
Automotive device grade 3:
– Temperature:
– Automotive grade certified.
3.3 V supply Flash memories
M58BW32FT: 8838h
M58BW16FT: 883Ah
M58BW32FB: 8837h
M58BW16FB: 8839h
10 x 8 ball array
LBGA80 (ZA)
PQFP80 (T)
40 to 125 °C
LBGA
M58BW16F
M58BW32F
Preliminary Data
www.st.com
1/87
1

Related parts for m58bw32f

m58bw32f Summary of contents

Page 1

... Program and Erase operations – PEN signal for Program/Erase Enable Irreversible modify protection (OTP like) on 128 Kbits: – Block 1 (bottom device) or block 72 (top device) in the M58BW32F – Blocks 2 and 3 (bottom device) or blocks 36 and 35 (top device) in the M58BW16F Security – 64-bit unique device identifier (UID) Fast programming – ...

Page 2

... SS SSQ Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . 24 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . 25 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M58BW16F, M58BW32F ...

Page 3

... M58BW16F, M58BW32F 3.1.7 3.1.8 3.2 Synchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 3.2.2 3.3 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7 Erase All Main Blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.8 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.9 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 ...

Page 4

... PEN Status (bit 5.6 Program Suspend Status (bit 5.7 Block Protection Status (bit 5.8 Bit Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Appendix A Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Appendix B Common Flash interface (CFI Appendix C Block protection Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4/87 M58BW16F, M58BW32F ...

Page 5

... CFI - Query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 30. CFI - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 31. M58BW16F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 32. M58BW16F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 33. M58BW32F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 34. M58BW32F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 35. Protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 List of tables 5/87 ...

Page 6

... Command interface and Program/Erase controller flowchart ( Figure 32. Command interface and Program/Erase controller flowchart ( Figure 33. Command interface and Program/Erase controller flowchart ( Figure 34. Command interface and Program/Erase controller flowchart ( Figure 35. Command interface and Program/Erase controller flowchart ( 6/87 M58BW16F, M58BW32F ...

Page 7

... On power-up the memory defaults to Read mode with an Asynchronous Bus. The device features an asymmetrical block architecture: The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128 Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW32FT the bottom (M58BW32FB) of the address space ...

Page 8

... Erase operations from affecting their data. A permanent user-enabled protection against Modify operations is available: – on one specific 128-Kbit parameter block in the M58BW32F – block 1 for bottom devices or block 72 for top devices – on two specific 64-Kbit parameter blocks in the M58BW16F – blocks 2 and 3 for bottom devices or blocks 36 and 35 for top devices ...

Page 9

... M58BW16F, M58BW32F Figure 1. Logic diagram DDQ V DDQIN (1) A0-Amax E K PEN L M58BW16F M58BW32F SSQ Description DQ0-DQ31 R AI13224b 9/87 ...

Page 10

... Power supply for input buffers only DDQIN PEN Program/Erase Enable V Ground SS V Input/output ground SSQ NC Not connected internally DU Don’t use as internally connected 1. Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. 10/87 Function M58BW16F, M58BW32F Direction Inputs I/O I/O I/O Input Input Input Input Input ...

Page 11

... LBGA connections (top view through package A15 B A16 C A17 D DQ3 E V DDQ F V SSQ G V DDQ H DQ13 J DQ15 K V DDQIN 1. Ball the M58BW16F and A19 in the M58BW32F A14 V DD PEN V SS A13 A12 A9 A8 A18 A11 A10 NC A19/ DQ0 NC NC (1) NC ...

Page 12

... DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 12/87 1 M58BW16F 12 M58BW32F 24 M58BW16F, M58BW32F DQ15 64 DQ14 DQ13 DQ12 V SSQ V DDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 53 DQ5 DQ4 V SSQ V DDQ DQ3 DQ2 DQ1 DQ0 (1) A19/NC ...

Page 13

... Permanent protection against modify operations - specific OTP-like blocks can be permanently protected against modify operations (Program/Erase): – in the M58BW32F, a unique 128-Kbit parameter block – block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices – in the M58BW16F, two 64-Kbit parameter blocks – blocks 2 and 3 (01000h- 01FFFh) for bottom devices or blocks 36 and 35 (7E000h-7EFFFh) for top devices This protection is user-enabled ...

Page 14

... Description Table 2. M58BW32F top boot block addresses # Size (Kbit 14/87 128 128 128 128 512 512 512 512 512 ...

Page 15

... M58BW16F, M58BW32F Table 2. M58BW32F top boot block addresses (continued) # Size (Kbit Addresses are indicated in 32-bit addressing. 2. OTP block. 512 512 512 512 512 ...

Page 16

... Description Table 3. M58BW32F bottom boot block addresses # 16/87 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 ...

Page 17

... M58BW16F, M58BW32F Table 3. M58BW32F bottom boot block addresses (continued Addresses are indicated in 32-bit word addressing. 2. OTP block. Size (Kbit) 512 512 512 512 ...

Page 18

... M58BW16F, M58BW32F Address range 7F800h-7FFFFh 7F000h-7F7FFh 7E800h-7EFFFh 7E000h-7E7FFh 7D800h-7DFFFh 7D000h-7D7FFh 7C800h-7CFFFh 7C000h-7C7FFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-5FFFFh 58000h-5BFFFh 54000h-57FFFh ...

Page 19

... M58BW16F, M58BW32F Table 5. M58BW16F bottom boot block addresses # ( OTP block. Size (Kbit) 512 512 512 512 512 512 512 512 ...

Page 20

... Address inputs (A0-Amax) Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. The Address inputs are used to select the cells to access in the memory array during Bus operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller ...

Page 21

... M58BW16F, M58BW32F 2.5 Output Disable (GD) The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD the outputs are driven by the Output Enable. When Output Disable, GD outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin ...

Page 22

... Latch Enable, whichever occurs first indicates that new data is or will be available. When Valid Data IH , the previous data outputs remain active. , the protection status that has been configured in the Block IL M58BW16F, M58BW32F . Once latched, the addresses may IL for Asynchronous Random Read IL , the internal address IL ...

Page 23

... M58BW16F, M58BW32F 2.14 Supply voltage (V The supply voltage, V the V pin, including the Program/Erase controller. DD 2.15 Output supply voltage (V The output supply voltage, V Program and Erase) used for DQ0-DQ31 when used as outputs. 2.16 Input supply voltage (V The input supply voltage GD A0-Amax and DQ0-DQ31, when used as inputs. ...

Page 24

... The read or Latch Enable, L, going Low Figure 7: Asynchronous Bus Read AC characteristics, for details of when and keeping Write Enable High read the data on the Data inputs/outputs; see IL IL M58BW16F, M58BW32F Chip IL . The IH ; the address is IH ...

Page 25

... M58BW16F, M58BW32F 3.1.3 Asynchronous Page Read Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the page buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings ...

Page 26

... M58BW16F, M58BW32F ) and the Data DD1 ) and the outputs are high DD1 A0-Amax Address Address ...

Page 27

... M58BW16F, M58BW32F 3.2 Synchronous Bus operations For Synchronous Bus Operations refer to access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, V 3.2.1 Synchronous Burst Read Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock ...

Page 28

... for examples of Synchronous Burst configurations. M58BW16F, M58BW32F , inhibits the data outputs. The Address input ...

Page 29

... M58BW16F, M58BW32F 3.3.3 X-Latency bits (M13-M11) The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock edges between the address being latched and the edge where the first data become available. For correct operation the X-Latency bits can only assume the values in Burst Configuration 3 ...

Page 30

... R valid Low during valid Burst Clock edge (default 0 value) R valid Low 1 data cycle before valid Burst Clock 1 edge 0 Reserved (default value) 1 Reserved 0 Falling Burst Clock edge (default value) 1 Rising Burst Clock edge 00 Reserved (default value) 01 Reserved 10 Reserved 11 Reserved 0 Wrap (default value Wrap M58BW16F, M58BW32F Description ...

Page 31

... X latencies can be calculated as: (t number from calculation latencies can be calculated as The M6 bit is Don’t care in the M58BW32F and the device has the Rising Burst Clock edge set. To maintain the compatibility this could be modified and read. Description Value ...

Page 32

... ADD VALID L DQ 3-1-1-1 DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 32/87 × 4 sequential 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 4-5-6-7 5-6-7-8 6-7-8-9 7-8-9-10 8-9-10- VALID VALID VALID VALID VALID VALID M58BW16F, M58BW32F × 8 sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 8-9-10-11-12-13-14- VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID 9 ...

Page 33

... M58BW16F, M58BW32F 4 Command interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. The commands are summarized in Table 10: descriptions below. 4.1 Read Memory Array command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode ...

Page 34

... Block Erase command. 34/87 and Output Disable and then reactivating it with Chip Enable and Output Enable Table 13 for details on the definitions of the Table 12. See Appendix A, M58BW16F, M58BW32F . IH the operation IH, Figure 28: Block Erase flowchart ...

Page 35

... M58BW16F, M58BW32F 4.7 Erase All Main Blocks command The Erase All Main Blocks command is used to erase all 63 main blocks, without affecting the parameter blocks. Issuing the Erase All Main Blocks command sets every bit in each main block to '1'. All data previously stored in the main blocks are lost. ...

Page 36

... Status Register and the Program/Erase Suspend commands. All other commands are ignored. If PEN operation aborts and the Status Register PEN bit (bit 3) is set to '1'. The Status Register should be cleared before re-issuing the command. 36/87 , the operation will be performed. If PEN is lower than V IH M58BW16F, M58BW32F the IH ...

Page 37

... M58BW16F, M58BW32F 4.10 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Erase operation. The command will only be accepted during a Program or Erase operation. It can be issued at any time during a Program or Erase operation. The command is ignored if the device is already in suspend mode. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase controller ...

Page 38

... Status Register with bits 4 and 5 set to ‘1’. To unprotect multiple blocks, the Clear Block Protection Configuration Register command must be repeated for each block. Any attempt to unprotect a block already unprotected does not affect its status. 38/87 M58BW16F, M58BW32F . The status of a protected IL ...

Page 39

... M58BW16F, M58BW32F (1) Table 10. Commands Command ≥ 2 Write Read Memory Array (2) ≥ 2 Write Read Electronic Signature Read Status Register 1 ≥ 2 Write Read Query Clear Status Register 1 Block Erase 2 Erase All Main Blocks 2 any block 2 Program OTP block 2 Write to Buffer and Program N+4 Write AAh E8h Write ...

Page 40

... M58BW16FB 00001h M58BW32FT 00001h M58BW32FB 00001h 00005h All SBA+02h M58BW16F Min Typ 0.8 0.6 45 (2) 100,000 = DDQ M58BW16F, M58BW32F DQ31-DQ0 00000020h 0000883Ah 00008839h 00008838h 00008837h (1) BCR 00000000h (Unprotected) (2) 00000001h (Protected) (1) M58BW32F Max Min Typ Max ...

Page 41

... M58BW16F, M58BW32F 5 Status Register The Status Register provides information on the current or previous Program, Erase or Block Protect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume commands ...

Page 42

... When bit 3 is set to ‘1’ a Program or Erase operation has been attempted with PEN Low, V Once set to ‘1’, bit 3 can only be reset by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 42/ M58BW16F, M58BW32F . IL ...

Page 43

... M58BW16F, M58BW32F 5.6 Program Suspend Status (bit 2) The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to ‘1’ (Program/Erase Controller inactive) ...

Page 44

... M58BW16F, M58BW32F Definition Ready Busy Suspended In progress or completed Erase error Erase success Program error Program success No program or erase attempted ...

Page 45

... M58BW16F, M58BW32F 6 Maximum rating Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...

Page 46

... Figure 6. AC measurement load circuit 46/87 conditions. Designers should check that the Parameter ) ) DDQ ) Grade DDQ V DDQIN 0 V DEVICE UNDER TEST C L includes JIG capacitance M58BW16F, M58BW32F M58BW16F, M58BW32F Min Max Min Max 2.7 3.6 2.5 3.3 2.4 3.6 2.4 3.6 –40 125 –40 125 30 30 ...

Page 47

... M58BW16F, M58BW32F Table 17. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT ° MHz Sampled only, not 100% tested. Table 18. DC characteristics Symbol I Input Leakage current LI I Output Leakage current LO Supply current (Random I DD Read) (1) I Supply current (power-up) ...

Page 48

... E G DQ0-DQ31 48/87 tAVAV VALID tAVQV tEHLX tELQX tELQV tGLQX tGLQV OUTPUT See also Page Read VALID tLHAX tLLLH tGLQX tGLQV tLLQV tLLQX M58BW16F, M58BW32F tAXQX tEHQX tEHQZ tGHQX tGHQZ AI08921b tEHLX tEHQX tEHQZ tGHQX GHQZ OUTPUT See also Page Read AI08922b ...

Page 49

... M58BW16F, M58BW32F Figure 9. Asynchronous Chip Enable Controlled Bus Read AC waveforms A0-A19 DQ0-DQ31 Figure 10. Asynchronous Address Controlled Bus Read AC waveforms A0-A19 DQ0-DQ31 VALID tLHAX tGLQX tGLQV tELQX tELQV VALID tLHAX tGLQX tGLQV tAVQV DC and AC parameters tEHLX tEHQX tEHQZ tGHQX GHQZ ...

Page 50

... after the falling edge of Chip Enable E without ELQV GLQV M58BW16F, M58BW32F M58BWxxF Min Max Min Min 0 0 Min ...

Page 51

... M58BW16F, M58BW32F Figure 11. Asynchronous Page Read AC waveforms A0-A1 DQ0-DQ31 Table 20. Asynchronous Page Read AC characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings see Table 19: Asynchronous Bus Read AC A0 and/or A1 tAVQV1 tAXQX OUTPUT + 1 OUTPUT (1) Test condition ...

Page 52

... DC and AC parameters Figure 12. Asynchronous Write AC waveforms 52/87 M58BW16F, M58BW32F ...

Page 53

... M58BW16F, M58BW32F Figure 13. Asynchronous Latch controlled Write AC waveforms DC and AC parameters 53/87 ...

Page 54

... Write Enable High to Output Enable Low WHGL t Write Enable High to Output Valid WHQV t Write Enable High to Write Enable Low WHWL t Write Enable Low to Write Enable High WLWH t Output Valid to Reset/Power-down Low QVPL 54/87 M58BW16F, M58BW32F M58BWxxF Test condition 45 Min 45 Min 8 Min Min ...

Page 55

... M58BW16F, M58BW32F Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’ clock rising edge) DC and AC parameters 55/87 ...

Page 56

... DC and AC parameters Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’ clock rising edge) 56/87 M58BW16F, M58BW32F ...

Page 57

... M58BW16F, M58BW32F Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid from ’n’ clock rising edge) DC and AC parameters 57/87 ...

Page 58

... Figure 18. Synchronous Burst Read - valid data ready output K (1) Output Valid Data Ready = Valid Low during valid clock edge Valid output. 3. The internal timing of R follows DQ. 58/87 n+1 n+2 n+3 n tKHQX Burst Read tRLKH (2) M58BW16F, M58BW32F n+5 Q5 AI04408c V AI03649b ...

Page 59

... M58BW16F, M58BW32F Figure 19. Synchronous Burst Read - Burst Address Advance K VALID A0-A19 L DQ0-DQ31 G B Figure 20. Clock input AC waveform K Q0 tGLQV tBLKH tKHKL tKLKH DC and AC parameters Q1 Q2 tBHKH AI03650 ai13286 59/87 ...

Page 60

... X-Latency = 3 M58BW16F X-Latency = M58BW32F characteristics. M58BW16F, M58BW32F M58BWxxF Unit 45 55 Max 40 33 MHz Max 56 40 MHz Max 75 56 MHz Min Min Min ...

Page 61

... M58BW16F, M58BW32F Figure 21. Power supply slope specification Voltage VDHH VDH 1. Please refer to the application note AN2601. Table 23. Power supply AC and DC characteristics Symbol V Minimum value of power supply ( Maximum value of power supply (V DHH t Time required from power supply to reach the V VDH 1. This threshold is 90% of the minimum value allowed to V ...

Page 62

... Figure 23. Reset, Power-down and Power-up AC waveforms - Control pins toggling Hi tVDHPH VDD, VDDQ 62/87 tPHWL tPHEL tPHGL tPHLL tPHRH Power-up tPHWL tPHEL tPHGL tPLRZ tPHLL tPHRH Power-up M58BW16F, M58BW32F Hi-Z tPLRZ tPHRH tPLPH Reset AI14239 tWLRH tGLRH tELRH tLLRH Hi-Z tPHRH tPLPH Reset AI14240 ...

Page 63

... M58BW16F, M58BW32F Table 24. Reset, Power-down and Power-up AC characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL t Reset/Power-down High to Latch Enable Low PHLL (1) t Reset/Power-down High to Output Valid PHQV t Reset/Power-down High to Write Enable Low PHWL t Reset/Power-down High to Output Enable Low PHGL t Reset/Power-down Low to Reset/Power-down High ...

Page 64

... ECOPACK trademark. ECOPACK specifications are available at: www.st.com. Figure 24. LBGA80 10 × × 10 ball array pitch, bottom view package outline Drawing is not to scale. 64/ BALL "A1" M58BW16F, M58BW32F SE ddd JE_ME ...

Page 65

... M58BW16F, M58BW32F Table 25. LBGA80 10 × × 10 active ball array pitch, package mechanical data Symbol ddd millimeters Typ Min Max 1.60 0.40 1.05 0.60 10.00 – – 7.00 – – 0.15 12.00 – – 9.00 – – 1.00 – – 1.50 – – 1.50 – – ...

Page 66

... M58BW16F, M58BW32F inches Typ Min 0.010 0.110 0.100 0.012 0.005 0.913 0.903 0.787 0.783 0.724 – 0.031 – 0.677 0.667 0.551 0.547 0.472 – 0.031 ...

Page 67

... M58BW16F, M58BW32F 9 Ordering information Table 27. Ordering information scheme Example: Device type M58 Architecture B = Burst mode Operating voltage Device function 32F = 32 Mbit (x 32), boot block, burst, 0.11 µm technology 16F = 16 Mbit (x 32), boot block, burst, 0.11 µm technology ...

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... PEN Invalid Error (1) NO Program Error (1) NO Program to Protect Block Error M58BW16F, M58BW32F Program command: – write 40h, Address AAh – write Address & Data (memory enters read status state after the Program command) do: – read status register ( must be toggled) ...

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... M58BW16F, M58BW32F Figure 27. Program Suspend & Resume flowchart and pseudocode Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block Write D0h Program Continues NO NO Program Complete Write FFh Read Data Flowcharts Program/Erase Suspend command: – ...

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... YES Command Sequence Error NO Erase Error (1) NO Erase to Protected Block Error M58BW16F, M58BW32F Erase command: – write 20h, Address 55h – write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command) do: – read status register ( must be toggled) ...

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... M58BW16F, M58BW32F Figure 29. Erase Suspend & Resume flowchart and pseudocode Erase cycle in progress Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program Write D0h Erase Continues NO NO Erase Complete Write FFh ...

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... Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read 72/87 M58BW16F, M58BW32F BCR bit 15 = '1' Set Burst Configuration Register command: – write 60h – write 03h and BCR on A15-A0 BCR bit 15 = '0' BCR bit 14-bit 0 = '1' ...

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... M58BW16F, M58BW32F Figure 31. Command interface and Program/Erase controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B NO YES NO 70h YES READ NO 20h STATUS YES ERASE SET-UP NO D0h YES A READ ARRAY D NO ...

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... Flowcharts Figure 32. Command interface and Program/Erase controller flowchart ( 48h YES TP 78h PROGRAM SET_UP F TP UNLOCK SET_UP G 74/87 NO YES NO 60h YES NO FFh SET BCR SET_UP YES NO 03h YES M58BW16F, M58BW32F D AI03836 ...

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... M58BW16F, M58BW32F Figure 33. Command interface and Program/Erase controller flowchart ( READ STATUS READ ARRAY YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS Flowcharts A ERASE YES READY NO NO READ B0h STATUS YES ERASE SUSPEND READY ...

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... Flowcharts Figure 34. Command interface and Program/Erase controller flowchart ( READ STATUS READ ARRAY 76/87 YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS M58BW16F, M58BW32F C PROGRAM READY NO NO READ B0h STATUS YES PROGRAM SUSPEND READY NO READ STATUS AI03838 ...

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... M58BW16F, M58BW32F Figure 35. Command interface and Program/Erase controller flowchart ( PROGRAM YES NO READ READY STATUS UNLOCK YES NO READ READY STATUS Flowcharts AI03839 77/87 ...

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... Description Manufacturer code ST M58BW16FT (top) M58BW16FB (bottom) Device code M58BW32FT (top) M58BW32FB (bottom) Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the primary algorithm (optional) Additional information specific to the alternate algorithm (optional) ...

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... Primary vendor: Command set and control interface ID code 00h 35h (M58BW16F) Primary algorithm extended query address table: 39h (M58BW32F) P(h) 00h 00h Alternate vendor: Command set and control interface ID code 00h 00h Alternate algorithm extended query address table ...

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... Erase Block region information x 256 bytes per Erase Block (64 Kbytes) 01h 07h Number (n-1) of Erase Blocks of identical size; n=8 00h 20h Erase Block region information x 256 bytes per Erase Block (8 Kbytes) 00h M58BW16F, M58BW32F Value 2 Mbytes x 32 Async bytes 2 31 blocks 512 Kbits ...

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... M58BW16F, M58BW32F Table 32. M58BW16F extended query information Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h (P+9)h (P+A)h-(P+D)h (P+13)h-(P+40)h (P+41)h (P+42)h (P+43)h (P+44)h Address Data (hex) Amax-A0 35h 50 P 36h 52 R Query ASCII string - extended table 37h 49 Y 38h 31h Major revision number 39h 31h Minor revision number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0= no) ...

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... Common Flash interface (CFI) Table 33. M58BW32F device geometry definition Address A0-Amax 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 82/87 Data Description n 15h 2 number of bytes memory size 03h Device interface sync./async. ...

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... M58BW16F, M58BW32F Table 34. M58BW32F extended query information Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h (P+9)h (P+A)h-(P+D)h (P+13)h-(P+40)h (P+41)h (P+42)h (P+43)h (P+44)h Address Data (hex) Amax-A0 39h 50 P 3Ah 52 R Query ASCII string - extended table 3Bh 49 Y 3Ch 31h Major revision number 3Dh 31h Minor revision number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0= no) ...

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... Bits 7-0=physical low address 0x0 Bits 15-8=physical high 0x0 address Bits 23-16=’n’, 2n=Factory pre- 0x12 programmed bytes 0x12 Bits 31-24=’n’, 2n=user programmable bytes M58BW16F, M58BW32F Value M58BW32FT M58BW16FT M58BW16FB M58BW32FB 128 128 ...

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... The OTP protection is an user-enabled feature that permanently protects specific blocks, so called “OTP blocks”, against modify operations (program/erase available: on one specific 128-kbit parameter block in the M58BW32F- block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices on two specific 64-kbit parameter blocks in the M58BW16F- block 2 and 3 (01000h- 01FFFh) for bottom devices or block 36 and 35 (7E000h-7EFFFh) for top devices ...

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... Table 22: KHQV characteristics. Figure 9, Figure added. Double Word Program max Table 12: cycles. characteristics. t and Figure 7. Appendix B: Common Flash Register, Table 30: CFI - device and Table 33: M58BW32F device , t and t modified in Table 22: KLKH LLKH characteristics and t added in WLRH GLRH ELRH LLRH characteristics. 24. ...

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... M58BW16F, M58BW32F Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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