m58bw32f STMicroelectronics, m58bw32f Datasheet - Page 34

• Manufacturer Part Number: m58bw32f
• Description: 16 Or 32 Mbit X32, Boot Block, Burst 3.3v Supply Flash Memories
• Manufacturer: STMicroelectronics

Command interface
4.4
4.5
4.6
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Read Status Register command
The Read Status Register command is used to read the Status Register. One Bus Write
cycle is required to issue the Read Status Register command. Once the command is issued
subsequent Bus Read operations read the Status Register until another command is issued.
The Status Register information is present on the output data bus (DQ0-DQ7) when Chip
Enable E and Output Enable G are at V
An interactive update of the Status Register bits is possible by toggling Output Enable or
Output Disable. It is also possible during a Program or Erase operation, by de-activating the
device with Chip Enable at V
at V
The content of the Status Register may also be read at the completion of a Program, Erase
or Suspend operation. During a Block Erase or Program command, DQ7 indicates the
Program/Erase controller status. It is valid until the operation is completed or suspended.
See the section on the Status Register and
Status Register bits.
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One Bus Write is required to issue the Clear Status Register command.
Once the command is issued the memory returns to its previous mode, subsequent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new
Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs
then it is essential to clear any error bits in the Status Register by issuing the Clear Status
Register command before attempting a new Program, Erase or Resume command.
Block Erase command
The Block Erase command can be used to erase a block. It sets all of the bits in the block to
‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will
abort, the data in the block will not be changed and the Status Register will output the error.
Two Bus Write operations are required to issue the command; the first write cycle sets up
the Block Erase command, the second write cycle confirms the Block Erase command and
latches the block address in the Program/Erase controller and starts the Program/Erase
controller. The sequence is aborted if the Confirm command is not given and the device will
output the Status Register Data with bits 4 and 5 set to '1'.
Once the command is issued subsequent Bus Read operations read the Status Register.
See the section on the Status Register for details on the definitions of the Status Register
bits. During the Erase operation the memory will only accept the Read Status Register
command and the Program/Erase Suspend command. All other commands will be ignored.
If PEN is at V
aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re-
issued.
Typical Erase times are given in
and
IL
pseudocode, for a suggested flowchart on using the Block Erase command.
and Output Disable at V
IH
, the operation can be performed. If PEN goes below V
IH
IH
and then reactivating it with Chip Enable and Output Enable
Table
.
12. See
IL
and Output Disable is at V
Table 13
Appendix
for details on the definitions of the
A,
Figure 28: Block Erase flowchart
M58BW16F, M58BW32F
IH
.
IH,
the operation