tmp88ch40img TOSHIBA Semiconductor CORPORATION, tmp88ch40img Datasheet - Page 15
tmp88ch40img
Manufacturer Part Number
tmp88ch40img
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CH40IMG.pdf
(148 pages)
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2. Functional Description
2.1 Functions of the CPU Core
2.1.1 Memory Address Map
The CPU core consists mainly of the CPU, system clock control circuit, and interrupt control circuit.
This chapter describes the CPU core, program memory, data memory, and reset circuit of the TMP88CH40IMG.
ROM: Read-Only Memory
RAM: Random Access Memory
ters), and DBR (Data Buffer Registers), which are mapped into one 1-Mbyte address space. The general-pur-
pose registers consist of 16 banks, which are mapped into the RAM address space. Figure 2-1 shows a memory
address map of the
The memory of the TMP88CH40IMG consists of four blocks: ROM, RAM, SFR (Special Function Regis-
ROM
(
RAM
(
DBR
16K
SFR
RAM
(128 bytes)
512
Program memory
Vector Table
Data memory
Stack
General-purpose register bank
bytes)
Kbytes)
FFFFFH
FFF3FH
FFF7FH
000BFH
000C0H
01FFFH
07EFFH
FFF00H
FFF40H
FFF80H
00000H
0003FH
00040H
002BFH
04000H
01F80H
TMP88CH40IMG
16128
512
SFR: Special Function Registers
128
128 bytes
128 bytes
64 bytes
64 bytes
64 bytes
Figure 2-1 Memory address map
bytes
bytes
bytes
Input/output port
Peripheral hardware control register
Peripheral hardware status register
System control register
Interrupt control register
Program status word
.
Special Function Register
General-purpose Register Bank
(8 registers × 16 banks)
Random-Access Memory
Data Buffer Register
(peripheral hardware control register / status register)
Program Memory
Interrupt Vector Table
Vector Table for
Vector Call Instructions
Interrupt Vector Table
Page 7
DBR: Data Buffer Registers
Input/output port
Peripheral hardware control register
Peripheral hardware status register
TMP88CH40IMG
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