tmp88ch40img TOSHIBA Semiconductor CORPORATION, tmp88ch40img Datasheet - Page 32

• Manufacturer Part Number: tmp88ch40img
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.3 Interrupt Sequence
3. Interrupt Control Circuit
3.3 Interrupt Sequence
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
3.3.1 Interrupt acceptance processing is packaged as follows.
“0” by resetting or an instruction. Interrupt acceptance sequence requires 12 machine cycles (2.4 µs @20 MHz) after
the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 62/fc [s] at maximum (If the interrupt latch is set at the first machine cycle on
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
service program
1-machine cycle
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
15 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
a-1
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vec-
e. Read the RBS control code from the vector table, add its MSB(4bit) to the register bank selecter
f. Count up the interrupt nesting counter.
g. The instruction stored at the entry address of the interrupt service program is executed.
instruction
Execute
lowing interrupt.
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL.
Meanwhile, the stack pointer (SP) is decremented by 5.
tor table, is transferred to the program counter.
(RBS).
a
a+1
n
Interrupt acceptance
a
n-1
n-2
n-3 n-4
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b b+1 b+2
instruction
Execute
n-5
b+3
c+1
Interrupt service task
n-4
Execute RETI instruction
n-3
c+2
n-2 n-1
TMP88CH40IMG
a
a+1 a+2
n