tmp88ch40img TOSHIBA Semiconductor CORPORATION, tmp88ch40img Datasheet - Page 20
tmp88ch40img
Manufacturer Part Number
tmp88ch40img
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CH40IMG.pdf
(148 pages)
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2.1 Functions of the CPU Core
2. Functional Description
2.1.4.3
Table 2-1 Single Clock Mode
system clock. The System Control Registers (SYSCR2) are used to control operation modes of this cir-
cuit. Figure 2-6 shows an operation mode transition diagram, followed by description of the System Con-
trol Registers.
Standby Control Circuit
(1)
The Standby Control Circuit starts/stops the high-frequency clock oscillator circuit and selects the main
Single
Clock
mode
IDLE
Operation Mode
ated from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s].
Single clock mode
Only the high-frequency clock oscillator circuit is used. Because the main system clock is gener-
RESET
NORMAL
IDLE
1. NORMAL mode
2. IDLE mode
Figure 2-6 Operation Mode Transition Diagram
quency clock. The TMP88CH40IMG enters this NORMAL mode after reset.
units are operated with the high-frequency clock. IDLE mode is entered into by using System
Control Register 2. The device is placed out of this mode and back into NORMAL mode by
an interrupt from the peripheral hardware or an external interrupt. When IMF (interrupt mas-
ter enable flag) = 1 (interrupt enabled), the device returns to normal operation after the inter-
rupt has been serviced. When IMF = 0 (interrupt disabled), the device restarts execution
beginning with the instruction next to one that placed it in IDLE mode.
In this mode, the CPU core and peripheral hardware units are operated with the high-fre-
In this mode, the CPU and watchdog timer are turned off while the peripheral hardware
Instruction
Interrupt
Frequency
Oscillate
High
Oscillator Circuit
Frequency
Low
-
NORMAL
Page 12
RESET
mode
Reset deasserted
CPU Core
Operate
Reset
Stop
Peripheral
Operate
Circuit
Reset
Machine Cycle
4/fc [s]
Time
TMP88CH40IMG
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