tmp88ch41ug TOSHIBA Semiconductor CORPORATION, tmp88ch41ug Datasheet - Page 34

• Manufacturer Part Number: tmp88ch41ug
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.1 Interrupt latches (IL39 to IL2)
3. Interrupt Control Circuit
Example 1 :Clears interrupt latches
Example 2 :Reads interrupt latches
Example 3 :Tests interrupt latches
3.1 Interrupt latches (IL39 to IL2)
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For
clearing the interrupt latch, load instruction should be used and then IL2 should be set to "1". If the read-modify-
write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared
inadequately if interrupt is requested while such instructions are executed.
latches are not set to “1” by an instruction.
Note 1: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
The interrupt latches are located on address 003CH, 003DH, 002EH, 002FH and 002BH in SFR area. Each latch
Since interrupt latches can be read, the status for interrupt requests can be monitored by software. But interrupt
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
-
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
reset is released). It is described in the section "Watchdog Timer" for details.
INT3 (External interrupt 3)
INT4 (External interrupt 4)
INTRX (UART receive interrupt)
INTTX (UART transmit interrupt)
INTSIO (SIO interrupt)
INTTC3 (TC3 interrupt)
INTTC4 (TC4 interrupt)
Reserved
INTADC (A/D converter interrupt)
INTVLTD
Interrupt Factors
DI
LD
LD
LD
LD
LD
EI
LD
LD
LD
TEST
JR
(ILL), 1110100000111111B
(ILH), 1110100000111111B
(ILE), 1110100000111111B
(ILD), 1110100000111111B
(ILC), 1110100000111111B
WA, (ILL)
BC, (ILE)
D, (ILC)
(ILL). 7
F, SSET
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IMF• EF30 = 1
IMF• EF31 = 1
IMF• EF32 = 1
IMF• EF33 = 1
IMF• EF34 = 1
IMF• EF35= 1
IMF• EF36 = 1
IMF• EF37 = 1
IMF• EF38 = 1
IMF• EF39 = 1
; IMF ← 0
; IL2 to IL7 ← 0
; IL8 to IL15 ← 0
; IL16 to IL23 ← 0
; IL24 to IL31 ← 0
; IL32 to IL39 ← 0
; IMF ← 1
; W ← (ILH), A ← (ILL)
; B ← (ILD), C ← (ILE)
; D ← (ILC)
; if IL7 = 1 then jump
Enable Condition
Interrupt
Latch
IL30
IL31
IL32
IL33
IL34
IL35
IL36
IL37
IL38
IL39
TMP88FH41UG
Address
FFF3C
FFF2C
FFF84
FFF80
FFF38
FFF34
FFF30
FFF28
FFF24
FFF20
Vector
Priority
Low 39
30
31
32
33
34
35
36
37
38