tmp88ch41ug TOSHIBA Semiconductor CORPORATION, tmp88ch41ug Datasheet - Page 71

• Manufacturer Part Number: tmp88ch41ug
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Watchdog Timer Control Register 1
Watchdog Timer Control Register 2
9.2.2 Watchdog Timer Enable
WDTCR1
WDTCR2
(0034H)
(0035H)
Note 1: After clearing WDTCR1<WDTOUT> to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
Note 5: To clear WDTCR1<WDTEN>, set the register in accordance with the procedures shown in “9.2.3 Watchdog Timer Dis-
Note 6: If the watchdog timer is disabled during watchdog timer interrupt processing, the watchdog timer interrupt will never be
Note 7: The watchdog timer consists of an internal divider and a two-stage binary counter. When clear code (4EH) is written, only
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code (4EH) using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
Note 5: WDTCR2 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR2 is read, a
to “1” during reset, the watchdog timer is enabled automatically after the reset release.
Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
WDTOUT
unknown data is read.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
able”.
cleared. Therefore, clear the watchdog timer ( set the clear code (4EH) to WDTCR2 ) before disabling it, or disable the
watchdog timer a sufficient time before it overflows.
the binary counter is cleared, not the internal divider.
Depending on the timing at which clear code (4EH) is written on the WDTCR2 register, the overflow time of the binary
counter may be at minimum 3/4 of the time set in WDTCR1<WDTT>. Thus, write the clear code using a shorter cycle than
3/4 of the time set in WDTCR1<WDTT>.
unknown data is read.
WDTEN
WDTCR2
WDTT
7
7
Watchdog timer enable/disable
Watchdog timer detection time
[s]
Watchdog timer output select
6
Write
Watchdog timer control code
6
5
5
4
4
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
0: Interrupt request
1: Reset request
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
Others: Invalid
3
00
01
10
11
WDTEN
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3
2
DV1CK = 0
2
2
2
2
2
25
23
19
21
WDTT
1
/fc
/fc
/fc
fc
1
NORMAL mode
0
WDTOUT
(Initial value: **** ****)
0
DV1CK = 1
(Initial value: **** 1001)
2
2
2
2
26
24
20
22
/fc
/fc
/fc
fc
TMP88FH41UG
Write
Write
Write
only
only
only
Write
only