atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 162
atmega32u4-16mu
Manufacturer Part Number
atmega32u4-16mu
Description
Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA32U4-16MU.pdf
(431 pages)
- Current page: 162 of 431
- Download datasheet (6Mb)
16.4
Output Compare Unit
The comparator continuously compares TCNT4 with the Output Compare Registers (OCR4A,
OCR4B, OCR4C and OCR4D). Whenever TCNT4 equals to the Output Compare Register, the
comparator signals a match. A match will set the Output Compare Flag (OCF4A, OCF4B or
OCF4D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Com-
pare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically
cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the PWM4x, WGM40 and Compare Out-
put mode (COM4x1:0) bits. The top and bottom signals are used by the Waveform Generator for
handling the special cases of the extreme values in some modes of operation
(See “Modes of
Operation” on page
168.).
Figure 16-4
shows a block diagram of the Output Compare unit.
Figure 16-4. Output Compare Unit, Block Diagram
8-BIT DATA BUS
OCRnx
TCnH
TCNTn
10-BIT OCRnx
10-BIT TCNTn
=
(10-bit Comparator )
OCFnx (Int.Req.)
TOP
PWMnx
Waveform Generator
BOTTOM
WGMn0
FOCn
COMnX1:0
OCWnx
The OCR4x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal mode of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR4x Compare Registers to either top or bottom of
the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym-
metrical PWM pulses, thereby making the output glitch-free. See
Figure 16-5
for an example.
During the time between the write and the update operation, a read from OCR4A, OCR4B,
OCR4C or OCR4D will read the contents of the temporary location. This means that the most
recently written value always will read out of OCR4A, OCR4B, OCR4C or OCR4D.
ATmega32U4
162
7766A–AVR–03/08
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