mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 424

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 11 Memory Mapping Control (S12XMMCV4) SUPPORTING FLEXRAY
11.4.2.1.1
Expansion of the CPU Local Address Map
The program page index register in MMC allows accessing up to 4MB of FLASH or ROM in the global
memory map by using the eight page index bits to page 256 16KB blocks into the program page window
located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64KB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper 16KB
block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and
interrupt vectors point to locations in this area or to the other unpaged sections of the local CPU memory
map.
Table 11-15
PPAGE register value and value of the ROMHM bit in the MMCCTL1 register.
The RAM page index register allows accessing up to 1MB minus 2KB of RAM in the global memory map
by using the eight RPAGE index bits to page 4KB blocks into the RAM page window located in the local
CPU memory space from address 0x1000 to address 0x1FFF. The EEPROM page index register EPAGE
allows accessing up to 256KB of EEPROM in the system by using the eight EPAGE index bits to page
1KB blocks into the EEPROM page window located in the local CPU memory space from address 0x0800
to address 0x0BFF.
424
Section 11.5.1, “CALL and RTC
summarizes mapping of the address bus in Flash/External space based on the address, the
Expansion of the Local Address Map
1. The internal or the external bus is accessed based on the size of the memory resources
implemented on-chip. Please refer to
0xC000–0xFFFF
0x4000–0x7FFF
0x8000–0xBFFF
CPU Address
Local
MC9S12XF - Family Reference Manual, Rev.1.19
Table 11-15. Global FLASH/ROM Allocated
ROMHM
Instructions).
N/A
N/A
N/A
0
1
Figure 1-23
External
Access
No
Yes
Yes
No
No
(1)
1
for further details.
0x7F_4000 –0x7F_7FFF
0x7F_C000–0x7F_FFFF
0x40_0000–0x7F_FFFF
0x14_4000–0x14_7FFF
Global Address
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