mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 75

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

1. 16 bits vector address based
2. For detailed description of XGATE channel ID refer to XGATE Block Guide
1.6.3
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block
descriptions for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers and
initialize the buffer RAM EEE partition, if required.
1.6.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers and
configuration from the Flash memory. The duration of this phase is given as tRST in the device electrical
parameter specification. If double faults are detected in the reset phase, Flash module protection and
security may be active on leaving reset. This is explained in more detail in the Flash (FTM) module section.
1.6.3.2
During this phase of the reset sequence (following on from the core hold phase) the CPU can execute
instructions while the FTM initialization completes and, if configured for EEE operation, the EEE RAM
is loaded with valid data from the D-Flash EEE partition. Completion of this phase is indicated by the
CCIF flag in the FTM FSTAT register becoming set. If the CPU accesses any EEE RAM location before
the CCIF flag is set, the CPU is stalled until the FTM reset sequence is complete and the EEE RAM data
is valid. Once the CCIF flag is set, indicating the end of this phase, the EEE RAM can be accessed without
impacting the CPU and FTM commands can be executed.
1.6.3.3
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
Refer to the PIM block description for reset configurations of all peripheral module ports.
Freescale Semiconductor
Vector Address
Vector base + $16
Vector base + $14
Vector base + $12
Vector base + $10
Effects of Reset
Flash Configuration Reset Sequence Phase (Core Hold Phase)
EEE Reset Sequence Phase (Core Active Phase)
Reset While Flash Command Active
I/O Pins
(1)
Channel ID
XGATE
—
—
—
—
Table 1-13. Interrupt Vector Locations (Sheet 4 of 4)
(2)
MC9S12XF - Family Reference Manual, Rev.1.19
XGATE software error interrupt
System Call Interrupt (SYS)
MPU Access Error
Spurious interrupt
Interrupt Source
Chapter 1 MC9S12XF-Family Reference Manual
Mask
None
None
CCR
—
—
Local Enable
None
None
None
None
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