mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 70

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 1 MC9S12XF-Family Reference Manual
1.4.1.5
Developers use this mode for emulation systems in which the user’s target application is normal single-
chip mode. Code is executed from external memory or from internal memory depending on the state of
ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.4.1.6
Freescale internal use only.
1.4.2
The MCU features two main low-power modes. Consult the respective module description for module
specific behavior in system stop, system pseudo stop, and system wait mode. An important source of
information about the clock system is the Clock and Reset Generator description (CRG).
1.4.2.1
The system stop modes are entered if the CPU executes the STOP instruction and the S bit in the CCR
register is cleared unless either the XGATE is active or an NVM command is active. The XGATE is active
if it executes a thread or the XGFACT bit in the XGMCTL register is set. Depending on the state of the
PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to
CRG description. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked causes the
system to exit the stop mode. System stop modes can be exited by XGATE or CPU activity independently,
depending on the configuration of the interrupt request. If System-Stop is exited on an XGATE request
then, as long as the XGATE does not set an interrupt flag on the CPU and the XGATE fake activity bit
(FACT) remains cleared, once XGATE activity is completed System Stop mode will automatically be re-
entered.
If the CPU executes the STOP instruction whilst XGATE is active or an NVM command is being
processed, then the system clocks continue running until XGATE/NVM activity is completed. If a non-
masked CPU-serviced interrupt occurs within this time then the system does not effectively enter stop
mode although the STOP instruction has been executed.
1.4.2.2
The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers
remain frozen. The Autonomous Periodic Interrupt (API) and ADC module may be enabled to self wake
the device. A Fast wake up mode is available to allow the device to wake from Full Stop mode immediately
on the PLL internal clock without starting the oscillator clock.
1.4.2.3
In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt
(RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This
mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed
wake up time from this mode is significantly shorter.
70
Power Modes
Emulation of Single-Chip Mode
Special Test Mode
System Stop Modes
Full Stop Mode
Pseudo Stop Mode
MC9S12XF - Family Reference Manual, Rev.1.19
Freescale Semiconductor