mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 921

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

20.3.2.20 PMF Enable Control A Register (PMFENCA)
Read and write anytime.
Freescale Semiconductor
Address: $0020
PWMRIEA
PMFVAL5
PWMENA
LDOKA
Reset
Field
Field
15–0
7
1
0
W
R
PWMENA
PMF Value 5 Bits — The 16-bit signed value in this buffered register is the pulse width in PWM5 clock period.
A value less than or equal to zero deactivates the PWM output for the entire PWM period. A value greater than,
or equal to the modulus, activates the PWM output for the entire PWM period. See
activate and deactivate refer to the high and low logic states of the PWM output.
Note: PMFVAL5 is buffered. The value written does not take effect until the LDOK bit is set and the next PWM
PWM Generator A Enable — When MTG is clear, this bit when set enables the PWM generators A, B and C
and the PWM0–5 pins. When PWMENA is clear, PWM generators A, B and C are disabled, and the PWM0–5
pins are in their inactive states unless the corresponding OUTCTLx bits are set.
When MTG is set, this bit when set enables the PWM generator A and the PWM0 and PWM1 pins. When
PWMENA is clear, the PWM generator A is disabled and PWM0 and PWM1 pins are in their inactive states
unless the OUTCTL0 and OUTCTL1 bits are set.
0 PWM generator A and PWM0-1 (2–5 if MTG = 0) pins disabled unless the respective OUTCTL bit is set.
1 PWM generator A and PWM0-1 (2–5 if MTG = 0) pins enabled.
Load Okay A — When MTG is clear, this bit allows loads of the PRSCA bits, the PMFMODA register and the
PWMVAL0-5 registers into a set of buffers. The buffered prescaler A divisor, PWM counter modulus A value, and
all PWM pulse widths take effect at the next PWM reload.
When MTG is set, this bit allows loads of the PRSCA bits, the PMFMODA register and the PWMVAL0–1 registers
into a set of buffers. The buffered prescaler divisor A, PWM counter modulus A value, PWM0–1 pulse widths take
effect at the next PWM reload.
Set LDOKA by reading it when it is logic zero and then writing a logic one to it. LDOKA is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKA.
0 Do not load new modulus A, prescaler A, and PWM0–1 (2–5 if MTG = 0) values
1 Load prescaler A, modulus A, and PWM0–1 (2–5 if MTG = 0) values
Note: Do not set PWMENA bit before setting the LDOKA bit and do not clear the LDOKA bit at the same time as
PWM Reload Interrupt Enable A — This bit enables the PWMRFA flag to generate CPU interrupt requests.
0 PWMRFA CPU interrupt requests disabled
1 PWMRFA CPU interrupt requests enabled
0
7
load cycle begins. Reading PMFVAL5 reads the value in the buffer and not necessarily the value the PWM
generator is currently using.
setting the PWMENA bit.
= Unimplemented or Reserved
Figure 20-26. PMF Enable Control A Register (PMFENCA)
0
0
6
MC9S12XF - Family Reference Manual, Rev.1.19
Table 20-24. PMFENCA Field Descriptions
Table 20-23. PMFVAL5 Field Descriptions
0
0
5
Chapter 20 Pulse Width Modulator with Fault Protection (PMF15B6C) Module
0
0
4
Description
Description
0
0
3
0
0
2
Table
LDOKA
20-36. The terms
0
1
PWMRIEA
0
0
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