mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 71

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

1.4.2.4
This mode is entered if the CPU executes the STOP instruction when the XGATE is not executing a thread
and the XGFACT bit in the XGMCTL register is set. The oscillator remains active and any enabled
peripherals continue to function.
1.4.2.5
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in
system wait mode. For further power consumption the peripherals can individually turn off their local
clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked and is not routed to XGATE
ends system wait mode.
1.4.2.6
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.4.3
The enhanced capture timer, COP, pulse width modulator, analog-to-digital converter, and the periodic
interrupt timer provide a software programmable option to freeze the module status when the background
debug module is active. This is useful when debugging application software. For detailed description of
the behavior of the ADC, ECT, COP and EPIT when the background debug module is active consult the
corresponding Block Guides.
1.5
The MCU security feature allows the protection of on chip NVM memories and RAM. For a detailed
description of the security features refer to the S12X9SEC description.
1.6
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1
Resets are explained in detail in the Clock Reset Generator (CRG) description.
1.6.2
Table 1-13
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module. IRQ is I-bit maskable and cannot be serviced by the XGATE.
Freescale Semiconductor
Security
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module
Freeze Mode
Resets
Vectors
XGATE Fake Activity Mode
Wait Mode
Run Mode
MC9S12XF - Family Reference Manual, Rev.1.19
Chapter 1 MC9S12XF-Family Reference Manual
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