mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 811

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

17.3.1.11 MPU Descriptor Register 5 (MPUDESC5)
1. These bits are intialized to the upper boundary of the MPU address range by a system reset. Depending on defined descriptor
Read: Anytime
Write: Anytime
17.4
The MPU module provides memory protection for accesses coming from multiple masters in the system.
This is done by monitoring bus traffic of each master and compare this with the configuration information
from a set of N
violation caused by the S12X CPU, it will assert the CPU access violation interrupt signal. If the MPU
detects an access violation caused by a bus master other than the S12X CPU, it raises an access error signal.
Please refer to the documentation chapter of the individual master modules (i.e. XGATE, etc.) for more
information about the access error condition.
Violating accesses are not executed. The return value of a violating read access is undefined for both 8 bit
and 16 bit accesses.
17.4.1
Each of the N protection descriptors can be used to restrict the allowed types of memory accesses for a
given memory range. Each of these memory ranges can cover up the entire defined MPU address range.
This can be the full 23 bits global memory range (8 MBytes) of the SoC.
1. The number of implemented descriptors is a configuration option defined at SoC level. Please refer to the MCU toplevel chapter
for details.
Freescale Semiconductor
Address: Module Base + 0x000B
HIGH_ADDR[
granularity and MPU address range some of these bits may not be writeable.
Reset
Field
10:3]
7–0
W
R
Functional Description
Protection Descriptors
1
Memory range upper boundary address bits — The HIGH_ADDR[10:3] bits represent bits [10:3] of the
global memory address that is used as the upper boundary for the described memory range. These bits are
intialized to the upper boundary of the MPU address range by a system reset.
7
(1)
Accesses from BDM are not restricted. BDM hardware accesses always
bypass the MPU. During execution of BDM firmware code S12X CPU
accesses are masked from the MPU as well.
1
programmable descriptors located in the MPU module. If the MPU detects an access
1
Figure 17-13. MPU Descriptor Register 5 (MPUDESC5)
6
1
Table 17-13. MPUDESC5 Field Descriptions
MC9S12XF - Family Reference Manual, Rev.1.19
1
5
1
HIGH_ADDR[10:3]
NOTE
1
4
1
Description
1
3
1
Chapter 17 Memory Protection Unit (S12XMPUV2)
1
2
1
1
1
1
1
0
1
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