mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 471

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mc9s12xf512

Manufacturer Part Number
mc9s12xf512
Description
S12x Microcontrollers 16-bit Automotive Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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13.5.2.4
This register defines the global configuration of the FlexRay block.
Freescale Semiconductor
Module Base + 0x0002
Reset
Write: MEN, SCM, CHB, CHA, CLKSEL, BITRATE: Disabled Mode
SCM CHB CHA
BITRATE
CLKSEL
12–11
W
SFFE
Field
MEN
SCM
CHB
CHA
R
3–1
15
13
10
R*
8
4
MEN
SFFE: Disabled Mode or
15
0
Module Enable — This bit indicates whether or not the FlexRay block is in the Disabled Mode. The application
requests the FlexRay block to leave the Disabled Mode by writing 1 to this bit. Before leaving the Disabled Mode,
the application must configure the SCM, CHB, CHA, TMODE, CLKSEL, BITRATE values. For details see
Section 13.1.6, “Modes of
0 Write: ignored, FlexRay block disable not possible
1 Write: enable FlexRay block
Note: If the FlexRay block is enabled it can not be disabled.
Single Channel Device Mode — This control bit defines the channel device mode of the FlexRay block as
described in
0 FlexRay block works in dual channel device mode
1 FlexRay block works in single channel device mode
Channel Enable — protocol related parameter:
The semantic of these control bits depends on the channel device mode controlled by the SCM bit and is given
Table
Synchronization Frame Filter Enable — This bit controls the filtering for received synchronization frames. For
details see
0 Synchronization frame filtering disabled
1 Synchronization frame filtering enabled
Reserved — This bit is reserved. It is read as 0. Application must not write 1 to this bit.
Protocol Engine Clock Source Select — This bit is used to select the clock source for the protocol engine.
0 PE clock source is generated by on-chip crystal oscillator.
1 PE clock source is generated by on-chip PLL.
FlexRay Bus Bit Rate — This bit field defines the bit rate of the flexray channels according to
Module Configuration Register (MCR)
14
0
0
Read: FlexRay block disabled
Read: FlexRay block enabled
13-9.
SCM
13
0
Section 13.6.15, “Sync Frame
Section 13.6.10, “Channel Device
CHB
12
Table 13-9. FlexRay Channel Selection (Sheet 1 of 2)
0
Figure 13-3. Module Configuration Register (MCR)
MC9S12XF - Family Reference Manual, Rev.1.19
CHA SFFE
11
POC:config
0
Operation”.
Table 13-8. MCR Field Descriptions
10
0
Dual Channel Device Modes
0
0
9
Filtering”.
R*
Modes”.
0
8
pChannels
Description
Description
0
0
7
Chapter 13 FlexRay Communication Controller (FLEXRAY)
6
0
0
0
0
5
CLKS
EL
0
4
0
3
BITRATE
0
2
Table
1
0
13-10.
0
0
0
471

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