m52s32321a Elite Semiconductor Memory Technology Inc., m52s32321a Datasheet - Page 10

• Manufacturer Part Number: m52s32321a
• Description: 512k X 32bit X 2banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
SIMPLIFIED TRUTH TABLE
Note:
Elite Semiconductor Memory Technology Inc.
Bank Active & Row Addr.
Refresh
Read &
Write & Column
Address
Precharge
Clock Suspend or
Precharge Power Down Mode
No Operation Command
Register
Column Address
Burst Stop
Active Power Down
DQM
Deep Power Down Mode
1. OP Code: Operation Code
2. MRS/EMRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA: Bank select address.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
A0~A10, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS.
A new command can be issued after 2 clock cycle of MRS.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks precharge state.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
COMMAND
Mode Register Set
Extended Mode Register
Set
Auto Refresh
Self Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
Entry
Exit
Entry
Exit
CKEn-1 CKEn CS
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RP
after the end of burst.
RAS
H
H
H
H
H
H
H
X
X
V
X
X
X
V
X
X
L
L
L
L
L
X
CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
H
X
L
L
L
L
L
WE
H
H
H
H
H
H
X
L
X
V
X
X
X
V
X
L
X
L
L
L
L
Revision : 1.5
Publication Date : Jan. 2009
DQM BA A10/AP A9~A0 Note
X
M52S32321A
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
V
V
V
V
X
OP CODE
OP CODE
Row Address
H
H
H
L
L
L
X
X
X
X
X
X
X
X
Address
(A0~A7)
Address
(A0~A7)
Column
Column
10/29
X
1,2
1,2
4,5
4,5
3
3
3
3
4
4
6
4
4
7